7,11c7,11
< host_inst_rate 110839 # Simulator instruction rate (inst/s)
< host_op_rate 121359 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47744278 # Simulator tick rate (ticks/s)
< host_mem_usage 278976 # Number of bytes of host memory used
< host_seconds 1554.53 # Real time elapsed on the host
---
> host_inst_rate 84730 # Simulator instruction rate (inst/s)
> host_op_rate 92772 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36497737 # Simulator tick rate (ticks/s)
> host_mem_usage 298520 # Number of bytes of host memory used
> host_seconds 2033.55 # Real time elapsed on the host
200,201c200,201
< system.physmem.totQLat 25205500 # Total ticks spent queuing
< system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 25203500 # Total ticks spent queuing
> system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM
204c204
< system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst
207c207
< system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst
236c236
< system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks)
238c238
< system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks)
240,241c240,241
< system.cpu.branchPred.lookups 94784279 # Number of BP lookups
< system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 94784274 # Number of BP lookups
> system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted
243c243
< system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups
246,247c246,247
< system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target.
295,301c295,301
< system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked
306c306
< system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched
---
> system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched
308c308
< system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total)
312c312
< system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total)
314c314
< system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total)
317c317
< system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total)
319,320c319,320
< system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total)
324c324
< system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total)
327,329c327,329
< system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running
---
> system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running
331,332c331,332
< system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch
---
> system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch
334c334
< system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode
336,337c336,337
< system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle
---
> system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle
339,342c339,342
< system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename
---
> system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename
344c344
< system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full
---
> system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full
346,349c346,349
< system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups
---
> system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups
352c352
< system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing
356c356
< system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit.
360c360
< system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec)
362,365c362,365
< system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph
367c367
< system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle
371c371
< system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle
373c373
< system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle
375c375
< system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle
377c377
< system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle
383c383
< system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle
419c419
< system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued
452c452
< system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued
456,457c456,457
< system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes
---
> system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes
462c462
< system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses
466c466
< system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed
475c475
< system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing
478c478
< system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ
480c480
< system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions
491c491
< system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute
500,501c500,501
< system.cpu.iew.wb_producers 148474079 # num instructions producing a value
< system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 148474078 # num instructions producing a value
> system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value
506c506
< system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit
509c509
< system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle
513,516c513,516
< system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle
525c525
< system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle
538,539c538,539
< system.cpu.rob.rob_reads 448787441 # The number of ROB reads
< system.cpu.rob.rob_writes 679451137 # The number of ROB writes
---
> system.cpu.rob.rob_reads 448787434 # The number of ROB reads
> system.cpu.rob.rob_writes 679451113 # The number of ROB writes
541c541
< system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling
577c577
< system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks.
579c579
< system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks.
584,589c584,589
< system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits
< system.cpu.icache.overall_hits::total 36845555 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits
> system.cpu.icache.overall_hits::total 36845557 # number of overall hits
596,607c596,607
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses
614,619c614,619
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency
640,645c640,645
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles
652,657c652,657
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
660c660
< system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use
666c666
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor
696,706c696,706
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles
731,741c731,741
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency
770,772c770,772
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles
775,780c775,780
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles
792,794c792,794
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency
797,802c797,802
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
835,838c835,838
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles
841,844c841,844
< system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles
867,870c867,870
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency
873,876c873,876
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency
905,912c905,912
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles
921,928c921,928
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
< host_inst_rate 110839 # Simulator instruction rate (inst/s)
< host_op_rate 121359 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47744278 # Simulator tick rate (ticks/s)
< host_mem_usage 278976 # Number of bytes of host memory used
< host_seconds 1554.53 # Real time elapsed on the host
---
> host_inst_rate 84730 # Simulator instruction rate (inst/s)
> host_op_rate 92772 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36497737 # Simulator tick rate (ticks/s)
> host_mem_usage 298520 # Number of bytes of host memory used
> host_seconds 2033.55 # Real time elapsed on the host
200,201c200,201
< system.physmem.totQLat 25205500 # Total ticks spent queuing
< system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 25203500 # Total ticks spent queuing
> system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM
204c204
< system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst
207c207
< system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst
236c236
< system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks)
238c238
< system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks)
240,241c240,241
< system.cpu.branchPred.lookups 94784279 # Number of BP lookups
< system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 94784274 # Number of BP lookups
> system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted
243c243
< system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups
246,247c246,247
< system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target.
295,301c295,301
< system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked
306c306
< system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched
---
> system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched
308c308
< system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total)
312c312
< system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total)
314c314
< system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total)
317c317
< system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total)
319,320c319,320
< system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total)
324c324
< system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total)
327,329c327,329
< system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running
---
> system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running
331,332c331,332
< system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch
---
> system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch
334c334
< system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode
336,337c336,337
< system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle
---
> system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle
339,342c339,342
< system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename
---
> system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename
344c344
< system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full
---
> system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full
346,349c346,349
< system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups
---
> system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups
352c352
< system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing
356c356
< system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit.
360c360
< system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec)
362,365c362,365
< system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph
367c367
< system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle
371c371
< system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle
373c373
< system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle
375c375
< system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle
377c377
< system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle
383c383
< system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle
419c419
< system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued
452c452
< system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued
456,457c456,457
< system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes
---
> system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes
462c462
< system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses
466c466
< system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed
475c475
< system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing
478c478
< system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ
480c480
< system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions
491c491
< system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute
500,501c500,501
< system.cpu.iew.wb_producers 148474079 # num instructions producing a value
< system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 148474078 # num instructions producing a value
> system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value
506c506
< system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit
509c509
< system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle
513,516c513,516
< system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle
525c525
< system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle
538,539c538,539
< system.cpu.rob.rob_reads 448787441 # The number of ROB reads
< system.cpu.rob.rob_writes 679451137 # The number of ROB writes
---
> system.cpu.rob.rob_reads 448787434 # The number of ROB reads
> system.cpu.rob.rob_writes 679451113 # The number of ROB writes
541c541
< system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling
577c577
< system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks.
579c579
< system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks.
584,589c584,589
< system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits
< system.cpu.icache.overall_hits::total 36845555 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits
> system.cpu.icache.overall_hits::total 36845557 # number of overall hits
596,607c596,607
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses
614,619c614,619
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency
640,645c640,645
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles
652,657c652,657
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
660c660
< system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use
666c666
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor
696,706c696,706
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles
731,741c731,741
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency
770,772c770,772
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles
775,780c775,780
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles
792,794c792,794
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency
797,802c797,802
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
835,838c835,838
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles
841,844c841,844
< system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles
867,870c867,870
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency
873,876c873,876
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency
905,912c905,912
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles
921,928c921,928
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency