7,11c7,11
< host_inst_rate 131550 # Simulator instruction rate (inst/s)
< host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 56674428 # Simulator tick rate (ticks/s)
< host_mem_usage 280244 # Number of bytes of host memory used
< host_seconds 1310.03 # Real time elapsed on the host
---
> host_inst_rate 44193 # Simulator instruction rate (inst/s)
> host_op_rate 48386 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19039219 # Simulator tick rate (ticks/s)
> host_mem_usage 236076 # Number of bytes of host memory used
> host_seconds 3899.58 # Real time elapsed on the host
73c73
< system.physmem.totGap 74245012500 # Total gap between requests
---
> system.physmem.totGap 74245013500 # Total gap between requests
167,168c167,168
< system.physmem.totQLat 12366785 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests
---
> system.physmem.totQLat 12368785 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests
171c171
< system.physmem.avgQLat 3260.42 # Average queueing delay per request
---
> system.physmem.avgQLat 3260.95 # Average queueing delay per request
174c174
< system.physmem.avgMemAccLat 22770.05 # Average memory access latency
---
> system.physmem.avgMemAccLat 22770.57 # Average memory access latency
187c187
< system.physmem.avgGap 19574218.96 # Average gap between requests
---
> system.physmem.avgGap 19574219.22 # Average gap between requests
242c242
< system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss
248,249c248,249
< system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
253,255c253,255
< system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total)
259c259
< system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total)
271c271
< system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total)
275c275
< system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked
287c287
< system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running
289c289
< system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename
294,296c294,296
< system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups
299c299
< system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing
314c314
< system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle
318c318
< system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle
330c330
< system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle
403c403
< system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads
426c426
< system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch
488c488
< system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling
503c503
< system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use
508c508
< system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor
517,534c517,534
< system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses
< system.cpu.icache.overall_misses::total 5339 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses
> system.cpu.icache.overall_misses::total 5340 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses
541,546c541,546
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency
555,560c555,560
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits
586,711d585
< system.cpu.dcache.replacements 57 # number of replacements
< system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
< system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
< system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
< system.cpu.dcache.overall_misses::total 9552 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
< system.cpu.dcache.writebacks::total 18 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
713c587
< system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use
719,720c593,594
< system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor
752,753c626,627
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles
757,758c631,632
< system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles
760,761c634,635
< system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles
791,792c665,666
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency
796,797c670,671
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency
799,800c673,674
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency
831,833c705,707
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles
838,843c712,717
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles
857,859c731,733
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency
864,869c738,743
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
870a745,870
> system.cpu.dcache.replacements 57 # number of replacements
> system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use
> system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
> system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
> system.cpu.dcache.overall_misses::total 9552 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
> system.cpu.dcache.writebacks::total 18 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< host_inst_rate 131550 # Simulator instruction rate (inst/s)
< host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 56674428 # Simulator tick rate (ticks/s)
< host_mem_usage 280244 # Number of bytes of host memory used
< host_seconds 1310.03 # Real time elapsed on the host
---
> host_inst_rate 44193 # Simulator instruction rate (inst/s)
> host_op_rate 48386 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 19039219 # Simulator tick rate (ticks/s)
> host_mem_usage 236076 # Number of bytes of host memory used
> host_seconds 3899.58 # Real time elapsed on the host
73c73
< system.physmem.totGap 74245012500 # Total gap between requests
---
> system.physmem.totGap 74245013500 # Total gap between requests
167,168c167,168
< system.physmem.totQLat 12366785 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests
---
> system.physmem.totQLat 12368785 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests
171c171
< system.physmem.avgQLat 3260.42 # Average queueing delay per request
---
> system.physmem.avgQLat 3260.95 # Average queueing delay per request
174c174
< system.physmem.avgMemAccLat 22770.05 # Average memory access latency
---
> system.physmem.avgMemAccLat 22770.57 # Average memory access latency
187c187
< system.physmem.avgGap 19574218.96 # Average gap between requests
---
> system.physmem.avgGap 19574219.22 # Average gap between requests
242c242
< system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss
248,249c248,249
< system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
253,255c253,255
< system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total)
259c259
< system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total)
271c271
< system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total)
275c275
< system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked
287c287
< system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running
289c289
< system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename
294,296c294,296
< system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups
299c299
< system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing
314c314
< system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle
318c318
< system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle
330c330
< system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle
403c403
< system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads
426c426
< system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch
488c488
< system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling
503c503
< system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use
508c508
< system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor
517,534c517,534
< system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses
< system.cpu.icache.overall_misses::total 5339 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses
> system.cpu.icache.overall_misses::total 5340 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses
541,546c541,546
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency
555,560c555,560
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits
586,711d585
< system.cpu.dcache.replacements 57 # number of replacements
< system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
< system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
< system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
< system.cpu.dcache.overall_misses::total 9552 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
< system.cpu.dcache.writebacks::total 18 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
713c587
< system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use
719,720c593,594
< system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor
752,753c626,627
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles
757,758c631,632
< system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles
760,761c634,635
< system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles
791,792c665,666
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency
796,797c670,671
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency
799,800c673,674
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency
831,833c705,707
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles
838,843c712,717
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles
857,859c731,733
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency
864,869c738,743
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency
870a745,870
> system.cpu.dcache.replacements 57 # number of replacements
> system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use
> system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
> system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
> system.cpu.dcache.overall_misses::total 9552 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
> system.cpu.dcache.writebacks::total 18 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate