7,11c7,11
< host_inst_rate 57710 # Simulator instruction rate (inst/s)
< host_op_rate 63186 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 25558377 # Simulator tick rate (ticks/s)
< host_mem_usage 235176 # Number of bytes of host memory used
< host_seconds 2986.21 # Real time elapsed on the host
---
> host_inst_rate 95790 # Simulator instruction rate (inst/s)
> host_op_rate 104880 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 42423254 # Simulator tick rate (ticks/s)
> host_mem_usage 235620 # Number of bytes of host memory used
> host_seconds 1799.08 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 246592 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 3853 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory
> system.physmem.bytes_read::total 246592 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s)
370a378
> system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses
371a380
> system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses
372a382
> system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses
373a384
> system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency
374a386
> system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency
375a388
> system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency
402a416
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses
403a418
> system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses
404a420
> system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses
405a422
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency
406a424
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
407a426
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
462a482
> system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
463a484
> system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses
464a486
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses
465a488
> system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses
466a490
> system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses
467a492
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency
468a494
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency
469a496
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency
470a498
> system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency
471a500
> system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency
508a538
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
509a540
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses
510a542
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
511a544
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
512a546
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency
513a548
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency
514a550
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
515a552
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
579a617
> system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses
580a619
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses
582a622
> system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses
584a625
> system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses
586a628
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency
587a630
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency
589a633
> system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency
591a636
> system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency
632a678
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses
633a680
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses
635a683
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses
637a686
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses
639a689
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency
640a691
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency
642a694
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
644a697
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
< host_inst_rate 57710 # Simulator instruction rate (inst/s)
< host_op_rate 63186 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 25558377 # Simulator tick rate (ticks/s)
< host_mem_usage 235176 # Number of bytes of host memory used
< host_seconds 2986.21 # Real time elapsed on the host
---
> host_inst_rate 95790 # Simulator instruction rate (inst/s)
> host_op_rate 104880 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 42423254 # Simulator tick rate (ticks/s)
> host_mem_usage 235620 # Number of bytes of host memory used
> host_seconds 1799.08 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 246592 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 3853 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory
> system.physmem.bytes_read::total 246592 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s)
370a378
> system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses
371a380
> system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses
372a382
> system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses
373a384
> system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency
374a386
> system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency
375a388
> system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency
402a416
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses
403a418
> system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses
404a420
> system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses
405a422
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency
406a424
> system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
407a426
> system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
462a482
> system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
463a484
> system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses
464a486
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses
465a488
> system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses
466a490
> system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses
467a492
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency
468a494
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency
469a496
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency
470a498
> system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency
471a500
> system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency
508a538
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
509a540
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses
510a542
> system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
511a544
> system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
512a546
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency
513a548
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency
514a550
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
515a552
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
579a617
> system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses
580a619
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses
582a622
> system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses
584a625
> system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses
586a628
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency
587a630
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency
589a633
> system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency
591a636
> system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency
632a678
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses
633a680
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses
635a683
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses
637a686
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses
639a689
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency
640a691
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency
642a694
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
644a697
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency