3,5c3,5
< sim_seconds 0.086155 # Number of seconds simulated
< sim_ticks 86154694000 # Number of ticks simulated
< final_tick 86154694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.086149 # Number of seconds simulated
> sim_ticks 86149358000 # Number of ticks simulated
> final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 235949 # Simulator instruction rate (inst/s)
< host_op_rate 248729 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 117978801 # Simulator tick rate (ticks/s)
< host_mem_usage 272668 # Number of bytes of host memory used
< host_seconds 730.26 # Real time elapsed on the host
---
> host_inst_rate 240669 # Simulator instruction rate (inst/s)
> host_op_rate 253706 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 120331720 # Simulator tick rate (ticks/s)
> host_mem_usage 272336 # Number of bytes of host memory used
> host_seconds 715.93 # Real time elapsed on the host
16,37c16,37
< system.physmem.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 652480 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 193344 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory
< system.physmem.bytes_read::total 916864 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 652480 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 652480 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 10195 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 3021 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 7573354 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2244149 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 824563 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 10642067 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 7573354 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 7573354 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 7573354 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2244149 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 824563 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 10642067 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 14326 # Number of read requests accepted
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory
> system.physmem.bytes_read::total 916736 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 14324 # Number of read requests accepted
39c39
< system.physmem.readBursts 14326 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue
41c41
< system.physmem.bytesReadDRAM 916864 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM
44c44
< system.physmem.bytesReadSys 916864 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::0 1380 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 1375 # Per bank write bursts
51,52c51,52
< system.physmem.perBankRdBursts::2 5094 # Per bank write bursts
< system.physmem.perBankRdBursts::3 810 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 5101 # Per bank write bursts
> system.physmem.perBankRdBursts::3 808 # Per bank write bursts
59,61c59,61
< system.physmem.perBankRdBursts::10 355 # Per bank write bursts
< system.physmem.perBankRdBursts::11 347 # Per bank write bursts
< system.physmem.perBankRdBursts::12 322 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 354 # Per bank write bursts
> system.physmem.perBankRdBursts::11 348 # Per bank write bursts
> system.physmem.perBankRdBursts::12 320 # Per bank write bursts
83c83
< system.physmem.totGap 86154635500 # Total gap between requests
---
> system.physmem.totGap 86149299500 # Total gap between requests
90c90
< system.physmem.readPktSize::6 14326 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 14324 # Read request sizes (log2)
98,107c98,107
< system.physmem.rdQLenPdf::0 12786 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1082 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see
194,211c194,211
< system.physmem.bytesPerActivate::samples 8486 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 107.983974 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 86.597492 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 122.302837 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 5884 69.34% 69.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 2105 24.81% 94.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 256 3.02% 97.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 62 0.73% 97.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 39 0.46% 98.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 37 0.44% 98.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 16 0.19% 98.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 9 0.11% 99.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 78 0.92% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 8486 # Bytes accessed per row activation
< system.physmem.totQLat 1505073312 # Total ticks spent queuing
< system.physmem.totMemAccLat 1773685812 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 71630000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 105058.87 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation
> system.physmem.totQLat 1500750524 # Total ticks spent queuing
> system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst
213c213
< system.physmem.avgMemAccLat 123808.87 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst
222c222
< system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
224c224
< system.physmem.readRowHits 5836 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 5833 # Number of row buffer hits during reads
226c226
< system.physmem.readRowHitRate 40.74 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads
228,231c228,231
< system.physmem.avgGap 6013865.38 # Average gap between requests
< system.physmem.pageHitRate 40.74 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 51536520 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 27380925 # Energy for precharge commands per rank (pJ)
---
> system.physmem.avgGap 6014332.55 # Average gap between requests
> system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ)
234,248c234,248
< system.physmem_0.refreshEnergy 5189405520.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1121826120 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 276469440 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 12277996650 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 8345487360 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 9295531755 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 36669774810 # Total energy per rank (pJ)
< system.physmem_0.averagePower 425.627121 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 82968376764 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 533443000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2206916000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 34311542002 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 21733088112 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 444281236 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 26925423650 # Time in different power states
---
> system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ)
> system.physmem_0.averagePower 425.565010 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states
251c251
< system.physmem_1.readEnergy 20199060 # Energy for read commands per rank (pJ)
---
> system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ)
253,273c253,273
< system.physmem_1.refreshEnergy 885081600.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 198834810 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 51009600 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 1986610170 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 1389476160 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 18829930140 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 23375329815 # Total energy per rank (pJ)
< system.physmem_1.averagePower 271.318119 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 85585158757 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 101660000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 376638000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 77610163250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 3618418671 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 91210493 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 4356603586 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 85641138 # Number of BP lookups
< system.cpu.branchPred.condPredicted 68185958 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5937589 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 39953535 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 38189781 # Number of BTB hits
---
> system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ)
> system.physmem_1.averagePower 271.290305 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 85639426 # Number of BP lookups
> system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits
275,281c275,281
< system.cpu.branchPred.BTBHitPct 95.585487 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 3685328 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 81910 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 681706 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 653811 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 27895 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 40302 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches.
283c283
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
313c313
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
343c343
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
373c373
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
404,405c404,405
< system.cpu.pwrStateResidencyTicks::ON 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 172309389 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 172298717 # number of cpu cycles simulated
408,414c408,414
< system.cpu.fetch.icacheStallCycles 5689865 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 347272234 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 85641138 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 42528920 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 158389740 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 11889123 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 4257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416,421c416,421
< system.cpu.fetch.IcacheWaitRetryStallCycles 4192 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 78352490 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 18126 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 170032695 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.137046 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.057606 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total)
423,426c423,426
< system.cpu.fetch.rateDist::0 18322538 10.78% 10.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 30071394 17.69% 28.46% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 31619936 18.60% 47.06% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 90018827 52.94% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total)
430,458c430,458
< system.cpu.fetch.rateDist::total 170032695 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.497020 # Number of branch fetches per cycle
< system.cpu.fetch.rate 2.015399 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 17554898 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 18106153 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 121828666 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 6773205 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 5769773 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 11065170 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 189895 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 305047176 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 27240886 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 5769773 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 37541623 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 8963730 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 601187 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 108324902 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 8831480 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 277455959 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 13183896 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 3097230 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 842604 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 2610060 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 40707 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 26842 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 481461567 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1187957820 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 296507996 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 3005110 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle
> system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups
460c460
< system.cpu.rename.UndoneMaps 188484638 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing
462,477c462,477
< system.cpu.rename.tempSerializingInsts 23627 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13450862 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 33923289 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 14424821 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 2554501 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1823311 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 263831896 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 45982 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 214447255 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 5189742 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 82241924 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 216953797 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 766 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 170032695 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.261212 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.018500 # Number of insts issued each cycle
---
> system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle
479,485c479,485
< system.cpu.iq.issued_per_cycle::0 53222567 31.30% 31.30% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 36044522 21.20% 52.50% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 65538005 38.54% 91.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 13630055 8.02% 99.06% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1551450 0.91% 99.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 45818 0.03% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 278 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle
491c491
< system.cpu.iq.issued_per_cycle::total 170032695 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle
493,494c493,494
< system.cpu.iq.fu_full::IntAlu 35671912 66.13% 66.13% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 153261 0.28% 66.41% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available
515c515
< system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.42% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available
517,518c517,518
< system.cpu.iq.fu_full::SimdFloatCmp 35713 0.07% 66.48% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 264 0.00% 66.48% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available
520,521c520,521
< system.cpu.iq.fu_full::SimdFloatMisc 557 0.00% 66.48% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 40113 0.07% 66.56% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available
524,527c524,527
< system.cpu.iq.fu_full::MemRead 13911271 25.79% 92.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 3849843 7.14% 99.48% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 142059 0.26% 99.75% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 136275 0.25% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available
531,532c531,532
< system.cpu.iq.FU_type_0::IntAlu 167013253 77.88% 77.88% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 919503 0.43% 78.31% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued
553,556c553,556
< system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.32% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.32% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 165181 0.08% 78.40% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 245720 0.11% 78.52% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued
558c558
< system.cpu.iq.FU_type_0::SimdFloatMisc 460387 0.21% 78.77% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued
562,565c562,565
< system.cpu.iq.FU_type_0::MemRead 31297547 14.59% 93.49% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 13233764 6.17% 99.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 576685 0.27% 99.93% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemWrite 147618 0.07% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued
568,580c568,580
< system.cpu.iq.FU_type_0::total 214447255 # Type of FU issued
< system.cpu.iq.rate 1.244548 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 53942541 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.251542 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 654066032 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 344116098 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 204293302 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 3993456 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 2010644 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 1806352 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 266215456 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 2174340 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1590107 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued
> system.cpu.iq.rate 1.244603 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores
582,585c582,585
< system.cpu.iew.lsq.thread0.squashedLoads 6027145 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 7088 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1780187 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed
588,589c588,589
< system.cpu.iew.lsq.thread0.rescheduledLoads 25576 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 767 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked
591,594c591,594
< system.cpu.iew.iewSquashCycles 5769773 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 5628686 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 175497 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 263897928 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ
596,607c596,607
< system.cpu.iew.iewDispLoadInsts 33923289 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 14424821 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 23574 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 3848 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 168493 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 7088 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3148569 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3247440 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 6396009 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 207164807 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 30640004 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 7282448 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute
609,620c609,620
< system.cpu.iew.exec_nop 20050 # number of nop insts executed
< system.cpu.iew.exec_refs 43787631 # number of memory reference insts executed
< system.cpu.iew.exec_branches 44861497 # Number of branches executed
< system.cpu.iew.exec_stores 13147627 # Number of stores executed
< system.cpu.iew.exec_rate 1.202284 # Inst execution rate
< system.cpu.iew.wb_sent 206408899 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 206099654 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 129383753 # num instructions producing a value
< system.cpu.iew.wb_consumers 221651913 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.196102 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.583725 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 68705367 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 20111 # number of nop insts executed
> system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed
> system.cpu.iew.exec_branches 44861358 # Number of branches executed
> system.cpu.iew.exec_stores 13146949 # Number of stores executed
> system.cpu.iew.exec_rate 1.202341 # Inst execution rate
> system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 129381204 # num instructions producing a value
> system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit
622,625c622,625
< system.cpu.commit.branchMispredicts 5762801 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 158729167 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.144404 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.650562 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle
627,635c627,635
< system.cpu.commit.committed_per_cycle::0 74124112 46.70% 46.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 41154034 25.93% 72.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 22561648 14.21% 86.84% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 9505511 5.99% 92.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 3552884 2.24% 95.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 2129952 1.34% 96.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1300201 0.82% 97.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1012623 0.64% 97.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 3388202 2.13% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle
639c639
< system.cpu.commit.committed_per_cycle::total 158729167 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle
689,693c689,693
< system.cpu.commit.bw_lim_events 3388202 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 405691473 # The number of ROB reads
< system.cpu.rob.rob_writes 512028923 # The number of ROB writes
< system.cpu.timesIdled 10004 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 2276694 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 405673353 # The number of ROB reads
> system.cpu.rob.rob_writes 512011515 # The number of ROB writes
> system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling
696,706c696,706
< system.cpu.cpi 1.000037 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.000037 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.999963 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.999963 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 218765999 # number of integer regfile reads
< system.cpu.int_regfile_writes 114196362 # number of integer regfile writes
< system.cpu.fp_regfile_reads 2903942 # number of floating regfile reads
< system.cpu.fp_regfile_writes 2441736 # number of floating regfile writes
< system.cpu.cc_regfile_reads 708332294 # number of cc regfile reads
< system.cpu.cc_regfile_writes 229516818 # number of cc regfile writes
< system.cpu.misc_regfile_reads 57457287 # number of misc regfile reads
---
> system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 218762027 # number of integer regfile reads
> system.cpu.int_regfile_writes 114194444 # number of integer regfile writes
> system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads
> system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes
> system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads
> system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes
> system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads
708,715c708,715
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 72598 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.401142 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 41046057 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 73110 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 561.428765 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 556160500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.401142 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 72586 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor
725,733c725,733
< system.cpu.dcache.tags.tag_accesses 82390572 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 82390572 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 28659846 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28659846 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12341293 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12341293 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits
738,745c738,745
< system.cpu.dcache.demand_hits::cpu.data 41001139 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 41001139 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 41001503 # number of overall hits
< system.cpu.dcache.overall_hits::total 41001503 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 89304 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 89304 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 22994 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 22994 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits
> system.cpu.dcache.overall_hits::total 41000964 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses
750,765c750,765
< system.cpu.dcache.demand_misses::cpu.data 112298 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 112298 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 112414 # number of overall misses
< system.cpu.dcache.overall_misses::total 112414 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 1992894500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 1992894500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 247642499 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 247642499 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2317500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 2317500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 2240536999 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 2240536999 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 2240536999 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 2240536999 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28749150 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28749150 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses
> system.cpu.dcache.overall_misses::total 112371 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses)
768,769c768,769
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses)
774,777c774,777
< system.cpu.dcache.demand_accesses::cpu.data 41113437 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 41113437 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 41113917 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 41113917 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses
780,783c780,783
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses
786,799c786,799
< system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22315.848114 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 22315.848114 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10769.874706 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 10769.874706 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8913.461538 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8913.461538 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 19951.708837 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 19951.708837 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 19931.120670 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 19931.120670 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency
801c801
< system.cpu.dcache.blocked_cycles::no_targets 11146 # number of cycles access was blocked
---
> system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked
803c803
< system.cpu.dcache.blocked::no_targets 867 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked
805,811c805,811
< system.cpu.dcache.avg_blocked_cycles::no_targets 12.855825 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 72598 # number of writebacks
< system.cpu.dcache.writebacks::total 72598 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24877 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 24877 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14424 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 14424 # number of WriteReq MSHR hits
---
> system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks
> system.cpu.dcache.writebacks::total 72586 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits
814,821c814,821
< system.cpu.dcache.demand_mshr_hits::cpu.data 39301 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 39301 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 39301 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 39301 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64427 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 64427 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8570 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 8570 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses
824,831c824,831
< system.cpu.dcache.demand_mshr_misses::cpu.data 72997 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 72997 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 73110 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 73110 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1062486000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 1062486000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88387499 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 88387499 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles
834,837c834,837
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1150873499 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 1150873499 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1151842499 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 1151842499 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles
842,845c842,845
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses
848,851c848,851
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16491.315753 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16491.315753 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10313.593816 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10313.593816 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency
854,865c854,865
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.038317 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.038317 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15754.924073 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 15754.924073 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 53656 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.578461 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 78294727 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 54168 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 1445.405535 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 85384212500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.578461 # Average occupied blocks per requestor
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 53582 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor
871,872c871,872
< system.cpu.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
875,914c875,914
< system.cpu.icache.tags.tag_accesses 156759076 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 156759076 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 78294727 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 78294727 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 78294727 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 78294727 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 78294727 # number of overall hits
< system.cpu.icache.overall_hits::total 78294727 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 57727 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 57727 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 57727 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 57727 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 57727 # number of overall misses
< system.cpu.icache.overall_misses::total 57727 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 2248583426 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 2248583426 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 2248583426 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 2248583426 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 2248583426 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 2248583426 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 78352454 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 78352454 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 78352454 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 78352454 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 78352454 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 78352454 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000737 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000737 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000737 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000737 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000737 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000737 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38952.022901 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 38952.022901 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 38952.022901 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 38952.022901 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 38952.022901 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 93736 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 78288973 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 78288973 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 78288973 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 78288973 # number of overall hits
> system.cpu.icache.overall_hits::total 78288973 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 57655 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 57655 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 57655 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 57655 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 57655 # number of overall misses
> system.cpu.icache.overall_misses::total 57655 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 2247853926 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 2247853926 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked
916c916
< system.cpu.icache.blocked::no_mshrs 3241 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked
918c918
< system.cpu.icache.avg_blocked_cycles::no_mshrs 28.921938 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked
920,954c920,954
< system.cpu.icache.writebacks::writebacks 53656 # number of writebacks
< system.cpu.icache.writebacks::total 53656 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3558 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 3558 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 3558 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 3558 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 3558 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 3558 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54169 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 54169 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 54169 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 54169 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 54169 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 54169 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2054126952 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 2054126952 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2054126952 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 2054126952 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2054126952 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 2054126952 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37920.710222 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37920.710222 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37920.710222 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37920.710222 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified
---
> system.cpu.icache.writebacks::writebacks 53582 # number of writebacks
> system.cpu.icache.writebacks::total 53582 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified
958,959c958,959
< system.cpu.l2cache.prefetcher.pfSpanPage 1351 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
961,964c961,964
< system.cpu.l2cache.tags.tagsinuse 1796.196657 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 99029 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2833 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 34.955524 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks.
966,967c966,967
< system.cpu.l2cache.tags.occ_blocks::writebacks 1727.103732 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.092925 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor
969,972c969,972
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004217 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.109631 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 127 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id
974,975c974,975
< system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::4 60 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # Occupied blocks per task id
979c979
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 198 # Occupied blocks per task id
981,1065c981,1065
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007751 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4005715 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4005715 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 64715 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 64715 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 51058 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 51058 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 8400 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 8400 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43969 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 43969 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61680 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 61680 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 43969 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 70080 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 114049 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 43969 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 70080 # number of overall hits
< system.cpu.l2cache.overall_hits::total 114049 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10200 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 10200 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2794 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 2794 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 10200 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 3030 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 13230 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 10200 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 3030 # number of overall misses
< system.cpu.l2cache.overall_misses::total 13230 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 21058000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 21058000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1711516500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1711516500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 557966500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 557966500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1711516500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 579024500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 2290541000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1711516500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 579024500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 2290541000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 64715 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 64715 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 51058 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 51058 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 8636 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 8636 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54169 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 54169 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64474 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 64474 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 54169 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 73110 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 127279 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 54169 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 73110 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 127279 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027327 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.027327 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188300 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188300 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043335 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043335 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188300 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.041444 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.103945 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188300 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.041444 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.103945 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89228.813559 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89228.813559 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167795.735294 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167795.735294 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199701.682176 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199701.682176 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167795.735294 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 191097.194719 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 173132.350718 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167795.735294 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 191097.194719 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 173132.350718 # average overall miss latency
---
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007996 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165100 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4002973 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4002973 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 64701 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 64701 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 50991 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 50991 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 8404 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 8404 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43901 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 43901 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61671 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 61671 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 43901 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 70075 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 113976 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 43901 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 70075 # number of overall hits
> system.cpu.l2cache.overall_hits::total 113976 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 230 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 230 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10194 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 10194 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 10194 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 3023 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 13217 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 10194 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 3023 # number of overall misses
> system.cpu.l2cache.overall_misses::total 13217 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20353000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 20353000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1710678000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1710678000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 556147500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 556147500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1710678000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 576500500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 2287178500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1710678000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 576500500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 2287178500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 64701 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 64701 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 50991 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 50991 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 8634 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 8634 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54095 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 54095 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64464 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 64464 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 54095 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 73098 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 127193 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 54095 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 73098 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 127193 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.026639 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.026639 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188446 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188446 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043327 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043327 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188446 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.041355 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.103913 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188446 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.041355 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.103913 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88491.304348 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88491.304348 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167812.242496 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167812.242496 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199121.911923 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199121.911923 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 173048.233336 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 173048.233336 # average overall miss latency
1084,1113c1084,1113
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2053 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 2053 # number of HardPFReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10195 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10195 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2786 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2786 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 10195 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 3021 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 13216 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 10195 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 3021 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2053 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 15269 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99413611 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99413611 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19424000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19424000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1649486500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1649486500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 540711500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 540711500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1649486500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 560135500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 2209622000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1649486500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 560135500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99413611 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 2309035611 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2048 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 2048 # number of HardPFReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 229 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 229 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10189 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10189 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 10189 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 3014 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 13203 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 10189 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 3014 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2048 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 15251 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 98123639 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18771000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18771000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1648684500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1648684500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 538898000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 538898000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1648684500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 557669000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 2206353500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1648684500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 557669000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 2304477139 # number of overall MSHR miss cycles
1116,1126c1116,1126
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027212 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188207 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043211 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043211 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041321 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.103835 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188207 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041321 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188354 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043202 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043202 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses
1128,1148c1128,1148
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.119965 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 48423.580614 # average HardPFReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82655.319149 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82655.319149 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161793.673369 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161793.673369 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 194081.658291 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 194081.658291 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167192.947942 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161793.673369 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185413.935783 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 48423.580614 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151223.761281 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 253533 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 126274 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 943 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 942 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1150,1165c1150,1165
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 118642 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 64715 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 61539 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 2391 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 54169 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 64474 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161993 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218818 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 380811 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6900736 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9325312 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 16226048 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 2391 # Total snoops (count)
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 2398 # Total snoops (count)
1167,1169c1167,1169
< system.cpu.toL2Bus.snoop_fanout::samples 129670 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.088263 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.283705 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram
1171,1172c1171,1172
< system.cpu.toL2Bus.snoop_fanout::0 118226 91.17% 91.17% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 11443 8.82% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram
1177,1178c1177,1178
< system.cpu.toL2Bus.snoop_fanout::total 129670 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 253020500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks)
1180c1180
< system.cpu.toL2Bus.respLayer0.occupancy 81260982 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks)
1182c1182
< system.cpu.toL2Bus.respLayer1.occupancy 109669990 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks)
1184,1185c1184,1185
< system.membus.snoop_filter.tot_requests 14326 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 10488 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1190,1198c1190,1198
< system.membus.pwrStateResidencyTicks::UNDEFINED 86154694000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 14090 # Transaction distribution
< system.membus.trans_dist::ReadExReq 235 # Transaction distribution
< system.membus.trans_dist::ReadExResp 235 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 14091 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28651 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 28651 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 14094 # Transaction distribution
> system.membus.trans_dist::ReadExReq 229 # Transaction distribution
> system.membus.trans_dist::ReadExResp 229 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes)
1201c1201
< system.membus.snoop_fanout::samples 14326 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 14324 # Request fanout histogram
1205c1205
< system.membus.snoop_fanout::0 14326 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram
1210,1211c1210,1211
< system.membus.snoop_fanout::total 14326 # Request fanout histogram
< system.membus.reqLayer0.occupancy 18054137 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 14324 # Request fanout histogram
> system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks)
1213c1213
< system.membus.respLayer1.occupancy 77252283 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks)