3,5c3,5
< sim_seconds 0.071387 # Number of seconds simulated
< sim_ticks 71387376000 # Number of ticks simulated
< final_tick 71387376000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.084956 # Number of seconds simulated
> sim_ticks 84955935500 # Number of ticks simulated
> final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 91858 # Simulator instruction rate (inst/s)
< host_op_rate 96834 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 38058123 # Simulator tick rate (ticks/s)
< host_mem_usage 257304 # Number of bytes of host memory used
< host_seconds 1875.75 # Real time elapsed on the host
---
> host_inst_rate 135379 # Simulator instruction rate (inst/s)
> host_op_rate 142711 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 66749907 # Simulator tick rate (ticks/s)
> host_mem_usage 309000 # Number of bytes of host memory used
> host_seconds 1272.75 # Real time elapsed on the host
16,32c16,36
< system.physmem.bytes_read::cpu.inst 130496 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 111040 # Number of bytes read from this memory
< system.physmem.bytes_read::total 241536 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 130496 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 130496 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2039 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1735 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 3774 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1827998 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1555457 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3383455 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1827998 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1827998 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1827998 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1555457 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3383455 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 3774 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory
> system.physmem.bytes_read::total 322048 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 5032 # Number of read requests accepted
34c38
< system.physmem.readBursts 3774 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue
36c40
< system.physmem.bytesReadDRAM 241536 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM
39c43
< system.physmem.bytesReadSys 241536 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side
43,59c47,63
< system.physmem.neitherReadNorWriteReqs 60 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 313 # Per bank write bursts
< system.physmem.perBankRdBursts::1 214 # Per bank write bursts
< system.physmem.perBankRdBursts::2 128 # Per bank write bursts
< system.physmem.perBankRdBursts::3 306 # Per bank write bursts
< system.physmem.perBankRdBursts::4 297 # Per bank write bursts
< system.physmem.perBankRdBursts::5 299 # Per bank write bursts
< system.physmem.perBankRdBursts::6 265 # Per bank write bursts
< system.physmem.perBankRdBursts::7 217 # Per bank write bursts
< system.physmem.perBankRdBursts::8 243 # Per bank write bursts
< system.physmem.perBankRdBursts::9 220 # Per bank write bursts
< system.physmem.perBankRdBursts::10 282 # Per bank write bursts
< system.physmem.perBankRdBursts::11 189 # Per bank write bursts
< system.physmem.perBankRdBursts::12 184 # Per bank write bursts
< system.physmem.perBankRdBursts::13 208 # Per bank write bursts
< system.physmem.perBankRdBursts::14 212 # Per bank write bursts
< system.physmem.perBankRdBursts::15 197 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 395 # Per bank write bursts
> system.physmem.perBankRdBursts::1 288 # Per bank write bursts
> system.physmem.perBankRdBursts::2 188 # Per bank write bursts
> system.physmem.perBankRdBursts::3 388 # Per bank write bursts
> system.physmem.perBankRdBursts::4 399 # Per bank write bursts
> system.physmem.perBankRdBursts::5 367 # Per bank write bursts
> system.physmem.perBankRdBursts::6 381 # Per bank write bursts
> system.physmem.perBankRdBursts::7 279 # Per bank write bursts
> system.physmem.perBankRdBursts::8 314 # Per bank write bursts
> system.physmem.perBankRdBursts::9 341 # Per bank write bursts
> system.physmem.perBankRdBursts::10 369 # Per bank write bursts
> system.physmem.perBankRdBursts::11 260 # Per bank write bursts
> system.physmem.perBankRdBursts::12 244 # Per bank write bursts
> system.physmem.perBankRdBursts::13 279 # Per bank write bursts
> system.physmem.perBankRdBursts::14 295 # Per bank write bursts
> system.physmem.perBankRdBursts::15 245 # Per bank write bursts
78c82
< system.physmem.totGap 71387262500 # Total gap between requests
---
> system.physmem.totGap 84955621000 # Total gap between requests
85c89
< system.physmem.readPktSize::6 3774 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 5032 # Read request sizes (log2)
93,108c97,112
< system.physmem.rdQLenPdf::0 2817 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 790 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 125 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see
189,206c193,210
< system.physmem.bytesPerActivate::samples 730 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 328.591781 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 199.502533 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 324.063907 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 243 33.29% 33.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 162 22.19% 55.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 95 13.01% 68.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 41 5.62% 74.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 34 4.66% 78.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 29 3.97% 82.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 36 4.93% 87.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 21 2.88% 90.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 69 9.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 730 # Bytes accessed per row activation
< system.physmem.totQLat 27328250 # Total ticks spent queuing
< system.physmem.totMemAccLat 98090750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 18870000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7241.19 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation
> system.physmem.totQLat 114920157 # Total ticks spent queuing
> system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst
208,209c212,213
< system.physmem.avgMemAccLat 25991.19 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.38 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s
211c215
< system.physmem.avgRdBWSys 3.38 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s
217c221
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing
219c223
< system.physmem.readRowHits 3037 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 4343 # Number of row buffer hits during reads
221c225
< system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads
223,226c227,230
< system.physmem.avgGap 18915543.85 # Average gap between requests
< system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 68189011250 # Time in different power states
< system.physmem.memoryStateTime::REF 2383680000 # Time in different power states
---
> system.physmem.avgGap 16883072.54 # Average gap between requests
> system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states
> system.physmem.memoryStateTime::REF 2836600000 # Time in different power states
228c232
< system.physmem.memoryStateTime::ACT 812104750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 905088250 # Time in different power states
230,243c234,253
< system.membus.throughput 3383455 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 2699 # Transaction distribution
< system.membus.trans_dist::ReadResp 2699 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 60 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 60 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7668 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7668 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 241536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 241536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 241536 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 4574500 # Layer occupancy (ticks)
---
> system.membus.trans_dist::ReadReq 4821 # Transaction distribution
> system.membus.trans_dist::ReadResp 4821 # Transaction distribution
> system.membus.trans_dist::ReadExReq 211 # Transaction distribution
> system.membus.trans_dist::ReadExResp 211 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 5032 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 5032 # Request fanout histogram
> system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks)
245,246c255,256
< system.membus.respLayer1.occupancy 35380947 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
248,252c258,262
< system.cpu.branchPred.lookups 106458293 # Number of BP lookups
< system.cpu.branchPred.condPredicted 82706448 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 6339444 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 50217715 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 48291708 # Number of BTB hits
---
> system.cpu.branchPred.lookups 85925623 # Number of BP lookups
> system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits
254,256c264,266
< system.cpu.branchPred.BTBHitPct 96.164686 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 5164625 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 84625 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions.
342c352
< system.cpu.numCycles 142774753 # number of cpu cycles simulated
---
> system.cpu.numCycles 169911872 # number of cpu cycles simulated
345,359c355,368
< system.cpu.fetch.icacheStallCycles 44808389 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 429802861 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 106458293 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 53456333 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 91468493 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 12731388 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 5563 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 41753796 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1912042 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 142648266 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 3.160575 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.133574 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 12044332 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total)
361,369c370,373
< system.cpu.fetch.rateDist::0 53718645 37.66% 37.66% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 6357410 4.46% 42.11% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 10351894 7.26% 49.37% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 14920250 10.46% 59.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 10655390 7.47% 67.30% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 3891108 2.73% 70.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 7883355 5.53% 75.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 9310317 6.53% 82.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 25559897 17.92% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total)
372,400c376,405
< system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::total 142648266 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.745638 # Number of branch fetches per cycle
< system.cpu.fetch.rate 3.010356 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 37233141 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 23853545 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 68602562 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 6747325 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 6211693 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 15955000 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 160395 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 420485829 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 828178 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 6211693 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 42171212 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 18551410 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 713419 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 69222818 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 5777714 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 398176302 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 1614739 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 2816561 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 62575 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 202 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 691997012 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1704697725 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 425662370 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 3491733 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle
> system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups
402,419c407,424
< system.cpu.rename.UndoneMaps 399020083 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 28576 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 28600 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 15636023 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 44518617 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 18120521 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 7204434 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 5193927 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 353303303 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 50659 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 249217571 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 532732 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 170449002 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 473050896 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 5443 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 142648266 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.747077 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.881809 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle
421,429c426,434
< system.cpu.iq.issued_per_cycle::0 54008982 37.86% 37.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 21782256 15.27% 53.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 24530872 17.20% 70.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 16106640 11.29% 81.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 11858342 8.31% 89.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 6781839 4.75% 94.69% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 5090438 3.57% 98.26% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1742716 1.22% 99.48% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 746181 0.52% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
432,433c437,438
< system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::total 142648266 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle
435,465c440,470
< system.cpu.iq.fu_full::IntAlu 1599616 44.61% 44.61% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 5629 0.16% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 43 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 26 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 44.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 2425 0.07% 44.84% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 44.84% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.84% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 44.84% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 1462989 40.80% 85.64% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 515010 14.36% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available
469,499c474,504
< system.cpu.iq.FU_type_0::IntAlu 192832828 77.38% 77.38% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1041370 0.42% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.79% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 33133 0.01% 77.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.81% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 164691 0.07% 77.87% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 264054 0.11% 77.98% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 76936 0.03% 78.01% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 473853 0.19% 78.20% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 207040 0.08% 78.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 72084 0.03% 78.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 78.31% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 39374798 15.80% 94.11% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 14676461 5.89% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued
502,514c507,519
< system.cpu.iq.FU_type_0::total 249217571 # Type of FU issued
< system.cpu.iq.rate 1.745530 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 3585738 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.014388 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 641399049 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 521384383 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 237201307 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 3802829 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 2450137 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 1875104 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 250898873 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1904436 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 1999527 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued
> system.cpu.iq.rate 1.264818 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores
516,519c521,524
< system.cpu.iew.lsq.thread0.squashedLoads 16622473 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 18079 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 32569 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 5475887 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed
522,523c527,528
< system.cpu.iew.lsq.thread0.rescheduledLoads 334532 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 126 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked
525,541c530,546
< system.cpu.iew.iewSquashCycles 6211693 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 18514097 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 29892 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 353371291 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 723756 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 44518617 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 18120521 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 28251 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 2286 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 27735 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 32569 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3999566 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3827175 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 7826741 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 243157329 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 37609930 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 6060242 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute
543,551c548,556
< system.cpu.iew.exec_nop 17329 # number of nop insts executed
< system.cpu.iew.exec_refs 51859202 # number of memory reference insts executed
< system.cpu.iew.exec_branches 55857945 # Number of branches executed
< system.cpu.iew.exec_stores 14249272 # Number of stores executed
< system.cpu.iew.exec_rate 1.703084 # Inst execution rate
< system.cpu.iew.wb_sent 240511751 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 239076411 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 145760285 # num instructions producing a value
< system.cpu.iew.wb_consumers 269855272 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 15970 # number of nop insts executed
> system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed
> system.cpu.iew.exec_branches 44936358 # Number of branches executed
> system.cpu.iew.exec_stores 13142399 # Number of stores executed
> system.cpu.iew.exec_rate 1.221373 # Inst execution rate
> system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 129467920 # num instructions producing a value
> system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value
553,554c558,559
< system.cpu.iew.wb_rate 1.674501 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.540142 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back
556c561
< system.cpu.commit.commitSquashedInsts 171723245 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit
558,561c563,566
< system.cpu.commit.branchMispredicts 6185443 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 117932320 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.540293 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.243745 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle
563,571c568,576
< system.cpu.commit.committed_per_cycle::0 51372616 43.56% 43.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 31468321 26.68% 70.24% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 11935963 10.12% 80.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 6951478 5.89% 86.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 3813624 3.23% 89.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1418078 1.20% 90.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1525333 1.29% 91.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1616480 1.37% 93.36% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 7830427 6.64% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle
575c580
< system.cpu.commit.committed_per_cycle::total 117932320 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle
621c626
< system.cpu.commit.bw_lim_events 7830427 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached
623,626c628,631
< system.cpu.rob.rob_reads 463470278 # The number of ROB reads
< system.cpu.rob.rob_writes 731648814 # The number of ROB writes
< system.cpu.timesIdled 1645 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 126487 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 406255589 # The number of ROB reads
> system.cpu.rob.rob_writes 513821131 # The number of ROB writes
> system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling
629,639c634,644
< system.cpu.cpi 0.828626 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.828626 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.206817 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.206817 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 248213314 # number of integer regfile reads
< system.cpu.int_regfile_writes 133191535 # number of integer regfile writes
< system.cpu.fp_regfile_reads 2934311 # number of floating regfile reads
< system.cpu.fp_regfile_writes 2552498 # number of floating regfile writes
< system.cpu.cc_regfile_reads 830988511 # number of cc regfile reads
< system.cpu.cc_regfile_writes 255127381 # number of cc regfile writes
< system.cpu.misc_regfile_reads 66039150 # number of misc regfile reads
---
> system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 218958563 # number of integer regfile reads
> system.cpu.int_regfile_writes 114511116 # number of integer regfile writes
> system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads
> system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes
> system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads
> system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes
> system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads
641,717c646,734
< system.cpu.toL2Bus.throughput 5345035 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 4859 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 4858 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 61 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 61 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1087 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1087 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8146 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3823 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 11969 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 258688 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 118976 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 377664 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 377664 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3029000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 6522997 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 3106540 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu.icache.tags.replacements 2317 # number of replacements
< system.cpu.icache.tags.tagsinuse 1337.456920 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 41747829 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4039 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 10336.179500 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 1337.456920 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.653055 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.653055 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1722 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 83511695 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 83511695 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 41748272 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 41748272 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 41748272 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 41748272 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 41748272 # number of overall hits
< system.cpu.icache.overall_hits::total 41748272 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 5524 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5524 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5524 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5524 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5524 # number of overall misses
< system.cpu.icache.overall_misses::total 5524 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 227823494 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 227823494 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 227823494 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 227823494 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 227823494 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 227823494 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 41753796 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 41753796 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 41753796 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 41753796 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 41753796 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 41753796 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000132 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000132 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000132 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000132 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000132 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000132 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 41242.486242 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 41242.486242 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked
---
> system.cpu.toL2Bus.trans_dist::ReadReq 119664 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 119664 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 64873 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 8632 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 8632 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109774 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211691 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 321465 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3512768 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850048 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 7801 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 200978 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5.038815 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.193155 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 193177 96.12% 96.12% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 161464494 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.cpu.icache.tags.replacements 54375 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.661166 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997385 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 78896017 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 78896017 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 78896017 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 78896017 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 78896017 # number of overall hits
> system.cpu.icache.overall_hits::total 78896017 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 56806 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 56806 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 56806 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 56806 # number of overall misses
> system.cpu.icache.overall_misses::total 56806 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 474677200 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 474677200 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 474677200 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 474677200 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 474677200 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 78952823 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 78952823 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 78952823 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 78952823 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 78952823 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000719 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000719 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000719 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000719 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000719 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8356.110270 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked
719c736
< system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked
721c738
< system.cpu.icache.avg_blocked_cycles::no_mshrs 47.611111 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked
725,754c742,771
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1420 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1420 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1420 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1420 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1420 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1420 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4104 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4104 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4104 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4104 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4104 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4104 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164891501 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 164891501 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164891501 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 164891501 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164891501 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 164891501 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40178.240984 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40178.240984 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1919 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 1919 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 1919 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 1919 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 1919 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 1919 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54887 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 54887 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 54887 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 54887 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 54887 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 54887 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 380604754 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 380604754 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 380604754 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 380604754 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 380604754 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 380604754 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6934.333339 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6934.333339 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency
755a773,781
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 435044 # number of hwpf identified
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 3068 # number of hwpf that were already in mshr
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 422406 # number of hwpf that were already in the cache
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3291 # number of hwpf that were already in the prefetch queue
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 894 # number of hwpf removed because MSHR allocated
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 5385 # number of hwpf issued
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 26500 # number of hwpf spanning a virtual page
> system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
757,760c783,786
< system.cpu.l2cache.tags.tagsinuse 1935.733118 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2084 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2703 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.770995 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 3680.652694 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 181097 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 4769 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 37.973789 # Average number of references to valid blocks.
762,856c788,883
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.025142 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1410.130158 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 522.577818 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043034 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.015948 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.059074 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2703 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1935 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.082489 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 51495 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 51495 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2000 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 83 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2083 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 17 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 17 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 12 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 12 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 2000 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2095 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2000 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2095 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2043 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 672 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 2715 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 60 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 60 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2043 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1747 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 3790 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2043 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1747 # number of overall misses
< system.cpu.l2cache.overall_misses::total 3790 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 140715500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 47433250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 188148750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74164250 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 74164250 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 140715500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 121597500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 262313000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 140715500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 121597500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 262313000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 4043 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 4798 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 17 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 17 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1087 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1087 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 4043 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1842 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 5885 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4043 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1842 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 5885 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.505318 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890066 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.565861 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983607 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983607 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.988960 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.988960 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.505318 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.948426 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.644010 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.505318 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.948426 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.644010 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68876.896721 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70585.193452 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69299.723757 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68990 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68990 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68876.896721 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69603.606182 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69211.873351 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68876.896721 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69603.606182 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69211.873351 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 700.245747 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 217.753448 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 276.465568 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2486.187931 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.042740 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.013291 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.016874 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.151745 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.224649 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 3319 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 1450 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::2 648 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 26 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2491 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 987 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.202576 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.088501 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 3104105 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 3104105 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 54552 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 64413 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 118965 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 64873 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 64873 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 8421 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 8421 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 54552 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 72834 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 127386 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 54552 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 72834 # number of overall hits
> system.cpu.l2cache.overall_hits::total 127386 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 699 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 575 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 910 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 575 # number of overall misses
> system.cpu.l2cache.overall_misses::total 910 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24852997 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26184000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 51036997 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15318999 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 15318999 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 24852997 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 41502999 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 66355996 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 24852997 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 41502999 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 66355996 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 54887 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 64777 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 119664 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 64873 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 64873 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 8632 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 8632 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 54887 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 128296 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 54887 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 128296 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.006103 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.005619 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.005841 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.024444 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.024444 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.006103 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.007833 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.007093 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.006103 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.007833 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.007093 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74188.050746 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71934.065934 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73014.301860 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72601.890995 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72601.890995 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72918.676923 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72918.676923 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 2973 # number of cycles access was blocked
858c885
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 134 # number of cycles access was blocked
860c887
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.186567 # average number of cycles each access was blocked
864,924c891,955
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2040 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 660 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 2700 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 60 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 60 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2040 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1735 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 3775 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2040 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1735 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 3775 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114933000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38476250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153409250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 623553 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 623553 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60696250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60696250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114933000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99172500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 214105500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114933000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99172500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 214105500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.874172 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.562734 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983607 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983607 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.988960 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.988960 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.641461 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.641461 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56339.705882 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58297.348485 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56818.240741 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10392.550000 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10392.550000 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56461.627907 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56461.627907 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 50 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 50 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 50 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 285 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 5385 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 5385 # number of HardPFReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 285 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 552 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 285 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 552 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 5385 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 6222 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20480998 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22050750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42531748 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 326822301 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13544999 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13544999 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20480998 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 35595749 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 56076747 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20480998 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 35595749 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 382899048 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.005264 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005231 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
> system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.024444 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.024444 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.006524 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.048497 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71863.150877 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64664.956012 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67942.089457 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60691.235097 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64194.308057 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64194.308057 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66997.308244 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61539.544841 # average overall mshr miss latency
926,951c957,982
< system.cpu.dcache.tags.replacements 56 # number of replacements
< system.cpu.dcache.tags.tagsinuse 1395.016190 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 47368346 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1842 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 25715.714441 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 1395.016190 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.340580 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.340580 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 1786 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::4 1369 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.436035 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 94757994 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 94757994 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 34966407 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 34966407 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12356440 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12356440 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 545 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 545 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 22480 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 22480 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.replacements 72897 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.503812 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 41115488 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 560.087837 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 471699000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.503812 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999031 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999031 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 82528199 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 82528199 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 28728737 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28728737 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12341838 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12341838 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits
954,981c985,1012
< system.cpu.dcache.demand_hits::cpu.data 47322847 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 47322847 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 47323392 # number of overall hits
< system.cpu.dcache.overall_hits::total 47323392 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1942 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1942 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 7847 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 7847 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 9789 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9789 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9795 # number of overall misses
< system.cpu.dcache.overall_misses::total 9795 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 120282480 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 120282480 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 504727051 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 504727051 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 143500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 143500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 625009531 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 625009531 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 625009531 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 625009531 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 34968349 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 34968349 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 41070575 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 41070575 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 41070936 # number of overall hits
> system.cpu.dcache.overall_hits::total 41070936 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 89075 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 89075 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 22449 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 22449 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 121 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 121 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 111524 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 111524 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 111645 # number of overall misses
> system.cpu.dcache.overall_misses::total 111645 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 824002993 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 824002993 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 221780748 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 221780748 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2327000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 2327000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 1045783741 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 1045783741 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 1045783741 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 1045783741 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28817812 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28817812 # number of ReadReq accesses(hits+misses)
984,987c1015,1018
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 551 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 551 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22482 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 22482 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 482 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 482 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
990,1021c1021,1052
< system.cpu.dcache.demand_accesses::cpu.data 47332636 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 47332636 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 47333187 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 47333187 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000635 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000635 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.010889 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.010889 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71750 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71750 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63848.149045 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63809.038387 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 848 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 85 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 41182099 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 41182099 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 41182581 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 41182581 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003091 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.003091 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001816 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.001816 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.251037 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.251037 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked
1024,1075c1055,1106
< system.cpu.dcache.writebacks::writebacks 17 # number of writebacks
< system.cpu.dcache.writebacks::total 17 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1189 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1189 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6701 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 6701 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 7890 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 7890 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 7890 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 7890 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 753 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 753 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1146 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1146 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1899 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1899 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1903 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1903 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48859513 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 48859513 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76658945 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 76658945 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 305000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 305000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 125518458 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 125518458 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 125823458 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 125823458 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007260 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007260 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76250 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76250 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 64873 # number of writebacks
> system.cpu.dcache.writebacks::total 64873 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24343 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 24343 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13890 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 13890 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 38233 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 38233 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 38233 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64732 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 64732 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8559 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 8559 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 118 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 118 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 73291 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 73291 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 483955005 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 483955005 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74150498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 74150498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1036250 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1036250 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 558105503 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 558105503 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 559141753 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 559141753 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.244813 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.244813 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001783 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7476.286921 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7476.286921 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8663.453441 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8663.453441 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8781.779661 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8781.779661 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7614.925475 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 7614.925475 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7616.801114 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 7616.801114 # average overall mshr miss latency