3,5c3,5
< sim_seconds 0.074212 # Number of seconds simulated
< sim_ticks 74211770500 # Number of ticks simulated
< final_tick 74211770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.074209 # Number of seconds simulated
> sim_ticks 74208571000 # Number of ticks simulated
> final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 109728 # Simulator instruction rate (inst/s)
< host_op_rate 120142 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47260193 # Simulator tick rate (ticks/s)
< host_mem_usage 316324 # Number of bytes of host memory used
< host_seconds 1570.28 # Real time elapsed on the host
---
> host_inst_rate 109569 # Simulator instruction rate (inst/s)
> host_op_rate 119969 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 47190079 # Simulator tick rate (ticks/s)
> host_mem_usage 316768 # Number of bytes of host memory used
> host_seconds 1572.55 # Real time elapsed on the host
16,32c16,32
< system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 112000 # Number of bytes read from this memory
< system.physmem.bytes_read::total 243072 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1750 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 3798 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1766189 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1509195 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3275383 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1766189 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1766189 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1766189 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1509195 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3275383 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 3799 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory
> system.physmem.bytes_read::total 243264 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 3802 # Number of read requests accepted
34c34
< system.physmem.readBursts 3799 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 243136 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 243136 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side
45,46c45,46
< system.physmem.perBankRdBursts::1 215 # Per bank write bursts
< system.physmem.perBankRdBursts::2 132 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 216 # Per bank write bursts
> system.physmem.perBankRdBursts::2 134 # Per bank write bursts
49c49
< system.physmem.perBankRdBursts::5 299 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 300 # Per bank write bursts
51c51
< system.physmem.perBankRdBursts::7 218 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 217 # Per bank write bursts
53c53
< system.physmem.perBankRdBursts::9 214 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 215 # Per bank write bursts
58c58
< system.physmem.perBankRdBursts::14 219 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 218 # Per bank write bursts
78c78
< system.physmem.totGap 74211752000 # Total gap between requests
---
> system.physmem.totGap 74208552500 # Total gap between requests
85c85
< system.physmem.readPktSize::6 3799 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 3802 # Read request sizes (log2)
93,96c93,96
< system.physmem.rdQLenPdf::0 2838 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 780 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 138 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see
189,208c189,206
< system.physmem.bytesPerActivate::samples 252 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 398.476190 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 217.440190 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 401.372897 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 87 34.52% 34.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 58 23.02% 57.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 17 6.75% 64.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 5 1.98% 66.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 7 2.78% 69.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 8 3.17% 72.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4 1.59% 73.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 3 1.19% 75.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 63 25.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 252 # Bytes accessed per row activation
< system.physmem.totQLat 23847500 # Total ticks spent queuing
< system.physmem.totMemAccLat 100702500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 18995000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 57860000 # Total ticks spent accessing banks
< system.physmem.avgQLat 6277.31 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 15230.32 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation
> system.physmem.totQLat 30320750 # Total ticks spent queuing
> system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst
210c208
< system.physmem.avgMemAccLat 26507.63 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst
219c217
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
221c219
< system.physmem.readRowHits 3018 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 3030 # Number of row buffer hits during reads
223c221
< system.physmem.readRowHitRate 79.44 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads
225,230c223,232
< system.physmem.avgGap 19534549.09 # Average gap between requests
< system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined
< system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 3275383 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 2728 # Transaction distribution
< system.membus.trans_dist::ReadResp 2727 # Transaction distribution
---
> system.physmem.avgGap 19518293.66 # Average gap between requests
> system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states
> system.physmem.memoryStateTime::REF 2477800000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 867720500 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 3278112 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 2731 # Transaction distribution
> system.membus.trans_dist::ReadResp 2730 # Transaction distribution
233,237c235,239
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7597 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7597 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243072 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 243072 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 243072 # Total data (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 243264 # Total data (bytes)
239c241
< system.membus.reqLayer0.occupancy 4687500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks)
241c243
< system.membus.respLayer1.occupancy 35592500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks)
244,248c246,250
< system.cpu.branchPred.lookups 94795806 # Number of BP lookups
< system.cpu.branchPred.condPredicted 74795654 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 6279989 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 44691885 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 43051051 # Number of BTB hits
---
> system.cpu.branchPred.lookups 94830067 # Number of BP lookups
> system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits
250,252c252,254
< system.cpu.branchPred.BTBHitPct 96.328564 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 4354918 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 88426 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions.
338c340
< system.cpu.numCycles 148423542 # number of cpu cycles simulated
---
> system.cpu.numCycles 148417143 # number of cpu cycles simulated
341,349c343,351
< system.cpu.fetch.icacheStallCycles 39654967 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 380195915 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 94795806 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 47405969 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 80368300 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 27279262 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 7212539 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 5988 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps
352,356c354,358
< system.cpu.fetch.CacheLines 36848695 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1833193 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 148225221 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.802047 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.153051 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total)
358,366c360,368
< system.cpu.fetch.rateDist::0 68026374 45.89% 45.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 5263091 3.55% 49.44% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 10536182 7.11% 56.55% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 10285653 6.94% 63.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 8660137 5.84% 69.33% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 6544581 4.42% 73.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 6243734 4.21% 77.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 8007959 5.40% 83.36% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 24657510 16.64% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total)
370,396c372,398
< system.cpu.fetch.rateDist::total 148225221 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.638684 # Number of branch fetches per cycle
< system.cpu.fetch.rate 2.561561 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 45510679 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 5881311 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 74801618 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1201370 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 20830243 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 14327753 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 392767808 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 749358 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 20830243 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 50895494 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 723680 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 602483 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 70555782 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4617539 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 371309891 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 338990 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 3664355 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 631718613 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1588504211 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1506839397 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 3198087 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle
> system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups
398,415c400,417
< system.cpu.rename.UndoneMaps 333674474 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 25005 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 25002 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13030816 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 43005440 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 16429294 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 5701095 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 3639070 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 329189812 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 47090 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 249460239 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 787524 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 139505237 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 362363758 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1874 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 148225221 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.682981 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.761692 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle
417,425c419,427
< system.cpu.iq.issued_per_cycle::0 56054819 37.82% 37.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 22642547 15.28% 53.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 24806201 16.74% 69.83% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 20327492 13.71% 83.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 12550892 8.47% 92.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 6518173 4.40% 96.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 4029511 2.72% 99.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1113373 0.75% 99.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 182213 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle
429c431
< system.cpu.iq.issued_per_cycle::total 148225221 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle
431,461c433,463
< system.cpu.iq.fu_full::IntAlu 964965 38.34% 38.34% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 5593 0.22% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 99 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 49 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 1170821 46.51% 85.08% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 375623 14.92% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available
465,466c467,468
< system.cpu.iq.FU_type_0::IntAlu 194894311 78.13% 78.13% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 979316 0.39% 78.52% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued
485c487
< system.cpu.iq.FU_type_0::SimdFloatAdd 33075 0.01% 78.53% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued
487,492c489,494
< system.cpu.iq.FU_type_0::SimdFloatCmp 164356 0.07% 78.60% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 254647 0.10% 78.70% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 76432 0.03% 78.73% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 465549 0.19% 78.92% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 206388 0.08% 79.00% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued
494,495c496,497
< system.cpu.iq.FU_type_0::MemRead 38358541 15.38% 94.41% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 13955444 5.59% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued
498,510c500,512
< system.cpu.iq.FU_type_0::total 249460239 # Type of FU issued
< system.cpu.iq.rate 1.680732 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2517150 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.010090 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 646712991 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 466571759 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 237891174 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 3737382 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 2188885 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 1841279 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 250102160 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1875229 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 2007089 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued
> system.cpu.iq.rate 1.680956 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores
512,515c514,517
< system.cpu.iew.lsq.thread0.squashedLoads 13155956 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 11631 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18977 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 3784660 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed
518c520
< system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled
521,537c523,539
< system.cpu.iew.iewSquashCycles 20830243 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 18508 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 911 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 329253924 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 785902 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 43005440 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 16429294 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 24682 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 206 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18977 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3891616 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3758665 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 7650281 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 36855491 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 6499895 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute
539,547c541,549
< system.cpu.iew.exec_nop 17022 # number of nop insts executed
< system.cpu.iew.exec_refs 50506525 # number of memory reference insts executed
< system.cpu.iew.exec_branches 53424421 # Number of branches executed
< system.cpu.iew.exec_stores 13651034 # Number of stores executed
< system.cpu.iew.exec_rate 1.636939 # Inst execution rate
< system.cpu.iew.wb_sent 240787816 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 239732453 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 148473522 # num instructions producing a value
< system.cpu.iew.wb_consumers 267271209 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 17004 # number of nop insts executed
> system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed
> system.cpu.iew.exec_branches 53432662 # Number of branches executed
> system.cpu.iew.exec_stores 13649116 # Number of stores executed
> system.cpu.iew.exec_rate 1.637124 # Inst execution rate
> system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 148472463 # num instructions producing a value
> system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value
549,550c551,552
< system.cpu.iew.wb_rate 1.615192 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.555516 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back
552c554
< system.cpu.commit.commitSquashedInsts 140583033 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit
554,557c556,559
< system.cpu.commit.branchMispredicts 6126865 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 127394978 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.480992 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.186196 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle
559,567c561,569
< system.cpu.commit.committed_per_cycle::0 57713917 45.30% 45.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 31674198 24.86% 70.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 13788488 10.82% 80.99% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 7625423 5.99% 86.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4380329 3.44% 90.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1321262 1.04% 91.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1701589 1.34% 92.79% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1311888 1.03% 93.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 7877884 6.18% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle
571c573
< system.cpu.commit.committed_per_cycle::total 127394978 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle
582c584,619
< system.cpu.commit.bw_lim_events 7877884 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 144055022 76.35% 76.35% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 908940 0.48% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 76.83% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 76.85% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 76.85% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.08% 76.93% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.06% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.10% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.23% 77.33% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.44% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.48% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.48% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 29849484 15.82% 93.30% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction
> system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached
584,587c621,624
< system.cpu.rob.rob_reads 448765817 # The number of ROB reads
< system.cpu.rob.rob_writes 679447245 # The number of ROB writes
< system.cpu.timesIdled 2831 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 198321 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 448818394 # The number of ROB reads
> system.cpu.rob.rob_writes 679565858 # The number of ROB writes
> system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling
591,599c628,636
< system.cpu.cpi 0.861410 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.861410 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.160887 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.160887 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1079439987 # number of integer regfile reads
< system.cpu.int_regfile_writes 384873432 # number of integer regfile writes
< system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads
< system.cpu.fp_regfile_writes 2497165 # number of floating regfile writes
< system.cpu.misc_regfile_reads 64868455 # number of misc regfile reads
---
> system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads
> system.cpu.int_regfile_writes 384888160 # number of integer regfile writes
> system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads
> system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes
> system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads
601,613c638,650
< system.cpu.toL2Bus.throughput 5152821 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 4879 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 4878 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8203 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3730 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 11933 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 262464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119936 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 382400 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 382400 # Total data (bytes)
---
> system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
615c652
< system.cpu.toL2Bus.reqLayer0.occupancy 3006000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks)
617c654
< system.cpu.toL2Bus.respLayer0.occupancy 6511747 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks)
619c656
< system.cpu.toL2Bus.respLayer1.occupancy 3051239 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks)
621,625c658,662
< system.cpu.icache.tags.replacements 2374 # number of replacements
< system.cpu.icache.tags.tagsinuse 1347.666302 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 36843383 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4101 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 8983.999756 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2388 # number of replacements
> system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks.
627,631c664,668
< system.cpu.icache.tags.occ_blocks::cpu.inst 1347.666302 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.658040 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.658040 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1727 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
633,675c670,712
< system.cpu.icache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1040 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.843262 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 73701491 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 73701491 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 36843383 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 36843383 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 36843383 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 36843383 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 36843383 # number of overall hits
< system.cpu.icache.overall_hits::total 36843383 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 5312 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5312 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5312 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5312 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5312 # number of overall misses
< system.cpu.icache.overall_misses::total 5312 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 224724996 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 224724996 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 224724996 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 224724996 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 224724996 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 224724996 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 36848695 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 36848695 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 36848695 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 36848695 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 36848695 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 36848695 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000144 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000144 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000144 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000144 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000144 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000144 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42305.157380 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42305.157380 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 1646 # number of cycles access was blocked
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits
> system.cpu.icache.overall_hits::total 36845676 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses
> system.cpu.icache.overall_misses::total 5390 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked
679c716
< system.cpu.icache.avg_blocked_cycles::no_mshrs 86.631579 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked
683,712c720,749
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1210 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 1210 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 1210 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 1210 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 1210 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 1210 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4102 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4102 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4102 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4102 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4102 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4102 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167739253 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 167739253 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167739253 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 167739253 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167739253 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 167739253 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40892.065578 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40892.065578 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40892.065578 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40892.065578 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1270 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 1270 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 1270 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 1270 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 1270 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 1270 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4120 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4120 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4120 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency
715,718c752,755
< system.cpu.l2cache.tags.tagsinuse 1968.326603 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2138 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2737 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.781147 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 1966.490721 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2149 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2739 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.784593 # Average number of references to valid blocks.
720,724c757,761
< system.cpu.l2cache.tags.occ_blocks::writebacks 4.994032 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.493487 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839084 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043503 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 4.023907 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1424.627361 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839452 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043476 # Average percentage of cache occupancy
726,728c763,765
< system.cpu.l2cache.tags.occ_percent::total 0.060069 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2737 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::total 0.060013 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 2739 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
730,736c767,773
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 602 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1971 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083527 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 51624 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 51624 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2050 # number of ReadReq hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 607 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1969 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083588 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 51788 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 51788 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2061 # number of ReadReq hits
738,751c775,788
< system.cpu.l2cache.ReadReq_hits::total 2137 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 2050 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2145 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2050 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2145 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2052 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 690 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 2742 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_hits::total 2148 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 2061 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2158 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2061 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2158 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2059 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 2748 # number of ReadReq misses
754,805c791,842
< system.cpu.l2cache.demand_misses::cpu.inst 2052 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1761 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 3813 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2052 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1761 # number of overall misses
< system.cpu.l2cache.overall_misses::total 3813 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143127750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50855750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 193983500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72887500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 72887500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 143127750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 123743250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 266871000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 143127750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 123743250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 266871000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 4102 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 777 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 4879 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 4102 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1856 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 5958 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4102 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1856 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 5958 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.500244 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888031 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.562000 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.500244 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.948815 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.639980 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.500244 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.948815 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.639980 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69750.365497 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73703.985507 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 70745.258935 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68055.555556 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68055.555556 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69989.771833 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69750.365497 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70268.739353 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69989.771833 # average overall miss latency
---
> system.cpu.l2cache.demand_misses::cpu.inst 2059 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1760 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 3819 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2059 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1760 # number of overall misses
> system.cpu.l2cache.overall_misses::total 3819 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 142590000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 50403250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 192993250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74281750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 74281750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 142590000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 124685000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 267275000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 142590000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 124685000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 267275000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 4120 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 776 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 4896 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 19 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 19 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 4120 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1857 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 5977 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4120 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1857 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 5977 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.499757 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887887 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.561275 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990749 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.990749 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.499757 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.947765 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.638949 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.499757 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.947765 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.638949 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69252.064109 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73154.208999 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 70230.440320 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69357.376284 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69357.376284 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69985.598324 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69252.064109 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70843.750000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69985.598324 # average overall miss latency
814,825c851,862
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 2728 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2055 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 676 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 2731 # number of ReadReq MSHR misses
828,866c865,903
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1750 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 3799 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1750 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 3799 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117223750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41708750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158932500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59427500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59427500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117223750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101136250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 218360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117223750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101136250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 218360000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.873874 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559131 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.637630 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.637630 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1747 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 3802 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1747 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 3802 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116514500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41206750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 157721250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60687250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60687250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116514500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101894000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 218408500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116514500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101894000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 218408500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871134 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.557802 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990749 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.990749 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.636105 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.498786 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940765 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.636105 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56698.053528 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60956.730769 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57752.196997 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56664.098973 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56664.098973 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56698.053528 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58325.128792 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57445.686481 # average overall mshr miss latency
868,872c905,909
< system.cpu.dcache.tags.replacements 59 # number of replacements
< system.cpu.dcache.tags.tagsinuse 1407.038554 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 46795712 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1856 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 25213.206897 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 60 # number of replacements
> system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks.
874,876c911,913
< system.cpu.dcache.tags.occ_blocks::cpu.data 1407.038554 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.343515 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.343515 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy
878c915
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
880c917
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id
884,891c921,928
< system.cpu.dcache.tags.tag_accesses 93612504 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 93612504 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 34394263 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 34394263 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12356566 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12356566 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 22476 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 22476 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits
894,901c931,938
< system.cpu.dcache.demand_hits::cpu.data 46750829 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 46750829 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 46750829 # number of overall hits
< system.cpu.dcache.overall_hits::total 46750829 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1889 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1889 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 7721 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 7721 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits
> system.cpu.dcache.overall_hits::total 46756186 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses
904,911c941,948
< system.cpu.dcache.demand_misses::cpu.data 9610 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9610 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9610 # number of overall misses
< system.cpu.dcache.overall_misses::total 9610 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 119060977 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 119060977 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 479134996 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 479134996 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses
> system.cpu.dcache.overall_misses::total 9638 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles
914,919c951,956
< system.cpu.dcache.demand_miss_latency::cpu.data 598195973 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 598195973 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 598195973 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 598195973 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 34396152 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 34396152 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses)
922,923c959,960
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22478 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 22478 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses)
926,929c963,966
< system.cpu.dcache.demand_accesses::cpu.data 46760439 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46760439 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46760439 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46760439 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses
932,933c969,970
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses
940,943c977,980
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency
946,950c983,987
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62247.239646 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62247.239646 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 566 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked
954c991
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.454545 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked
958,963c995,1000
< system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
< system.cpu.dcache.writebacks::total 18 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1111 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 19 # number of writebacks
> system.cpu.dcache.writebacks::total 19 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits
966,985c1003,1022
< system.cpu.dcache.demand_mshr_hits::cpu.data 7754 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 7754 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 7754 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 7754 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 778 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52580511 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 52580511 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73988748 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 73988748 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126569259 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 126569259 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126569259 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 126569259 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles
994,1001c1031,1038
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency