Cross Reference: /gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10036:80e84beef3bb ) new ( 10038:7eccd14e2610 )

full compact

4,5c4,5
< sim_ticks 74219948500 # Number of ticks simulated
< final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 74219931000 # Number of ticks simulated
> final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 133200 # Simulator instruction rate (inst/s)
< host_op_rate 145842 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 57376166 # Simulator tick rate (ticks/s)
< host_mem_usage 253176 # Number of bytes of host memory used
< host_seconds 1293.57 # Real time elapsed on the host
---
> host_inst_rate 128899 # Simulator instruction rate (inst/s)
> host_op_rate 141133 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 55523526 # Simulator tick rate (ticks/s)
> host_mem_usage 273064 # Number of bytes of host memory used
> host_seconds 1336.73 # Real time elapsed on the host
24c24
< system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s)
26,29c26,29
< system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s)
31c31
< system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 74219930000 # Total gap between requests
---
> system.physmem.totGap 74219912500 # Total gap between requests
202,203c202,203
< system.physmem.totQLat 25203500 # Total ticks spent queuing
< system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 25208000 # Total ticks spent queuing
> system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst
224c224
< system.physmem.avgGap 19562448.60 # Average gap between requests
---
> system.physmem.avgGap 19562443.99 # Average gap between requests
227c227
< system.membus.throughput 3270711 # Throughput (bytes/s)
---
> system.membus.throughput 3270712 # Throughput (bytes/s)
238c238
< system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks)
240c240
< system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks)
243,247c243,247
< system.cpu.branchPred.lookups 94784274 # Number of BP lookups
< system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits
---
> system.cpu.branchPred.lookups 94784239 # Number of BP lookups
> system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits
249,250c249,250
< system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target.
251a252,272
> system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
272a294,314
> system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
295c337
< system.cpu.numCycles 148439898 # number of cpu cycles simulated
---
> system.cpu.numCycles 148439863 # number of cpu cycles simulated
298,306c340,348
< system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps
309,312c351,354
< system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total)
315,323c357,365
< system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total)
327c369
< system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total)
329,352c371,394
< system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups
---
> system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups
355c397
< system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing
358,363c400,405
< system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec)
365,368c407,410
< system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph
370,371c412,413
< system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle
374,382c416,424
< system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle
386c428
< system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle
388c430
< system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available
408,412c450,454
< system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available
417c459
< system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available
422c464
< system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued
451,452c493,494
< system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued
455,457c497,499
< system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued
< system.cpu.iq.rate 1.680523 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested
---
> system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued
> system.cpu.iq.rate 1.680522 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested
459,461c501,503
< system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses
465c507
< system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses
467c509
< system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores
469c511
< system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed
472c514
< system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed
478,484c520,526
< system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions
---
> system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions
486c528
< system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall
---
> system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall
489,494c531,536
< system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute
496,504c538,546
< system.cpu.iew.exec_nop 17196 # number of nop insts executed
< system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed
< system.cpu.iew.exec_branches 53426072 # Number of branches executed
< system.cpu.iew.exec_stores 13648456 # Number of stores executed
< system.cpu.iew.exec_rate 1.636760 # Inst execution rate
< system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 148474078 # num instructions producing a value
< system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 17197 # number of nop insts executed
> system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed
> system.cpu.iew.exec_branches 53426054 # Number of branches executed
> system.cpu.iew.exec_stores 13648437 # Number of stores executed
> system.cpu.iew.exec_rate 1.636759 # Inst execution rate
> system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 148473973 # num instructions producing a value
> system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value
506c548
< system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle
509c551
< system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit
511,514c553,556
< system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle
516,524c558,566
< system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle
528c570
< system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle
539c581
< system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached
541,544c583,586
< system.cpu.rob.rob_reads 448787434 # The number of ROB reads
< system.cpu.rob.rob_writes 679451113 # The number of ROB writes
< system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 448786959 # The number of ROB reads
> system.cpu.rob.rob_writes 679450685 # The number of ROB writes
> system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling
550,553c592,595
< system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads
< system.cpu.int_regfile_writes 384871783 # number of integer regfile writes
---
> system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads
> system.cpu.int_regfile_writes 384871537 # number of integer regfile writes
556c598
< system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads
558,560c600,602
< system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution
---
> system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution
564c606
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes)
566,567c608,609
< system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes)
569,570c611,612
< system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
---
> system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes)
572c614
< system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks)
574c616
< system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks)
576c618
< system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks)
578,582c620,624
< system.cpu.icache.tags.replacements 2394 # number of replacements
< system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2395 # number of replacements
> system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks.
584c626
< system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor
588,589c630,631
< system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
594,619c636,661
< system.cpu.icache.tags.tag_accesses 73705913 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 73705913 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits
< system.cpu.icache.overall_hits::total 36845557 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses
< system.cpu.icache.overall_misses::total 5337 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits
> system.cpu.icache.overall_hits::total 36845513 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses
> system.cpu.icache.overall_misses::total 5338 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 225943745 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 225943745 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 225943745 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 36850851 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 36850851 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 36850851 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 36850851 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 36850851 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 36850851 # number of overall (read+write) accesses
626,631c668,673
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency
646,657c688,699
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles
664,669c706,711
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency
672,673c714,715
< system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 1967.449595 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2163 # Total number of references to valid blocks.
675c717
< system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 0.791728 # Average number of references to valid blocks.
677,679c719,721
< system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 4.994097 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569547 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885951 # Average occupied blocks per requestor
691,693c733,735
< system.cpu.l2cache.tags.tag_accesses 51779 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 51779 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 51787 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 51787 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2074 # number of ReadReq hits
695c737
< system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 2162 # number of ReadReq hits
700c742
< system.cpu.l2cache.demand_hits::cpu.inst 2073 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 2074 # number of demand (read+write) hits
702,703c744,745
< system.cpu.l2cache.demand_hits::total 2169 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2073 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2170 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2074 # number of overall hits
705c747
< system.cpu.l2cache.overall_hits::total 2169 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 2170 # number of overall hits
717,719c759,761
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51387250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 194615500 # number of ReadReq miss cycles
722,728c764,770
< system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 143228250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 123679500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 266907750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 143228250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 123679500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 266907750 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 4127 # number of ReadReq accesses(hits+misses)
730c772
< system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 4900 # number of ReadReq accesses(hits+misses)
735c777
< system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 4127 # number of demand (read+write) accesses
737,738c779,780
< system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 5979 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4127 # number of overall (read+write) accesses
740,741c782,783
< system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 5979 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497456 # miss rate for ReadReq accesses
743c785
< system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.558776 # miss rate for ReadReq accesses
746c788
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497456 # miss rate for demand accesses
748,749c790,791
< system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.637063 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497456 # miss rate for overall accesses
751,754c793,796
< system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.637063 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546 # average ReadReq miss latency
757,762c799,804
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70072.919401 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70072.919401 # average overall miss latency
791,793c833,835
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117257250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42300250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159557500 # number of ReadReq MSHR miss cycles
796,802c838,844
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117257250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101142000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 218399250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117257250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101142000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 218399250 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for ReadReq accesses
804c846
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555714 # mshr miss rate for ReadReq accesses
807c849
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses
809,810c851,852
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses
812,815c854,857
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407 # average ReadReq mshr miss latency
818,823c860,865
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency
826,827c868,869
< system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks.
829c871
< system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks.
831c873
< system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor
841,844c883,886
< system.cpu.dcache.tags.tag_accesses 93593418 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 93593418 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits
851,856c893,898
< system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits
< system.cpu.dcache.overall_hits::total 46741275 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits
> system.cpu.dcache.overall_hits::total 46741245 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses
861,866c903,908
< system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses
< system.cpu.dcache.overall_misses::total 9625 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses
> system.cpu.dcache.overall_misses::total 9623 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles
871,876c913,918
< system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses)
883,886c925,928
< system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses
897,898c939,940
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency
903,906c945,948
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency
917,918c959,960
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits
923,926c965,968
< system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits
935,936c977,978
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles
939,942c981,984
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles
951,952c993,994
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency
955,958c997,1000
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency