1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.076323 # Number of seconds simulated
4sim_ticks 76322764500 # Number of ticks simulated
5final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.076323 # Number of seconds simulated
4sim_ticks 76322764500 # Number of ticks simulated
5final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 160991 # Simulator instruction rate (inst/s)
8host_op_rate 176268 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 71299389 # Simulator tick rate (ticks/s)
10host_mem_usage 228164 # Number of bytes of host memory used
11host_seconds 1070.45 # Real time elapsed on the host
| 7host_inst_rate 57710 # Simulator instruction rate (inst/s)
8host_op_rate 63186 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 25558377 # Simulator tick rate (ticks/s)
10host_mem_usage 235176 # Number of bytes of host memory used
11host_seconds 2986.21 # Real time elapsed on the host
|
12sim_insts 172333279 # Number of instructions simulated
13sim_ops 188686762 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 246592 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 3853 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
38system.cpu.dtb.read_accesses 0 # DTB read accesses
39system.cpu.dtb.write_accesses 0 # DTB write accesses
40system.cpu.dtb.inst_accesses 0 # ITB inst accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.inst_hits 0 # ITB inst hits
45system.cpu.itb.inst_misses 0 # ITB inst misses
46system.cpu.itb.read_hits 0 # DTB read hits
47system.cpu.itb.read_misses 0 # DTB read misses
48system.cpu.itb.write_hits 0 # DTB write hits
49system.cpu.itb.write_misses 0 # DTB write misses
50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.itb.read_accesses 0 # DTB read accesses
60system.cpu.itb.write_accesses 0 # DTB write accesses
61system.cpu.itb.inst_accesses 0 # ITB inst accesses
62system.cpu.itb.hits 0 # DTB hits
63system.cpu.itb.misses 0 # DTB misses
64system.cpu.itb.accesses 0 # DTB accesses
65system.cpu.workload.num_syscalls 400 # Number of system calls
66system.cpu.numCycles 152645530 # number of cpu cycles simulated
67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups
70system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted
71system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect
72system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups
73system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits
74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
75system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target.
76system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions.
77system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss
78system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed
79system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered
80system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken
81system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked
82system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing
83system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked
84system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
85system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps
86system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
87system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched
88system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed
89system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total)
98system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total)
101system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total)
106system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle
107system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle
108system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle
109system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked
110system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running
111system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking
112system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing
113system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch
114system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction
115system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode
116system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode
117system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing
118system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle
119system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking
120system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst
121system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running
122system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking
123system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename
124system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
125system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full
126system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full
127system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed
128system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made
129system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups
130system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups
131system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed
132system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing
133system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed
134system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed
135system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer
136system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit.
137system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit.
138system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads.
139system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores.
140system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec)
141system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ
142system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued
143system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued
144system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling
145system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph
146system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed
147system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle
148system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle
155system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle
158system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle
159system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle
160system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
161system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
163system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle
164system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
165system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available
166system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available
167system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available
168system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available
169system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available
170system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available
171system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available
172system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available
173system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
174system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available
193system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
194system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available
195system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available
196system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
197system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
198system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
199system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued
200system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued
201system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
202system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
203system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
204system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued
205system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued
206system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued
207system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued
208system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued
227system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued
228system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued
229system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued
230system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
231system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
232system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued
233system.cpu.iq.rate 1.659274 # Inst issue rate
234system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested
235system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst)
236system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads
237system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes
238system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses
239system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads
240system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes
241system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses
242system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses
243system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses
244system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores
245system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
246system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed
247system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed
248system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations
249system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed
250system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
251system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
252system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled
253system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
254system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
255system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing
256system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking
257system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking
258system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ
259system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch
260system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions
261system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions
262system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions
263system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall
264system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall
265system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations
266system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly
267system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly
268system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute
269system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions
270system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed
271system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute
272system.cpu.iew.exec_swp 0 # number of swp insts executed
273system.cpu.iew.exec_nop 58893 # number of nop insts executed
274system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed
275system.cpu.iew.exec_branches 54101167 # Number of branches executed
276system.cpu.iew.exec_stores 13816344 # Number of stores executed
277system.cpu.iew.exec_rate 1.612486 # Inst execution rate
278system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit
279system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back
280system.cpu.iew.wb_producers 150184249 # num instructions producing a value
281system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value
282system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
283system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle
284system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back
285system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
286system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions
287system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions
288system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit
289system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards
290system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted
291system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle
292system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle
299system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle
302system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle
303system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle
304system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
305system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
307system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle
308system.cpu.commit.committedInsts 172347667 # Number of instructions committed
309system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed
310system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
311system.cpu.commit.refs 42506219 # Number of memory references committed
312system.cpu.commit.loads 29855535 # Number of loads committed
313system.cpu.commit.membars 22408 # Number of memory barriers committed
314system.cpu.commit.branches 40287733 # Number of branches committed
315system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
316system.cpu.commit.int_insts 150130425 # Number of committed integer instructions.
317system.cpu.commit.function_calls 1848934 # Number of function calls committed.
318system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached
319system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
320system.cpu.rob.rob_reads 458778355 # The number of ROB reads
321system.cpu.rob.rob_writes 693498788 # The number of ROB writes
322system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself
323system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling
324system.cpu.committedInsts 172333279 # Number of Instructions Simulated
325system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated
326system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated
327system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction
328system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads
329system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle
330system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads
331system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads
332system.cpu.int_regfile_writes 388952433 # number of integer regfile writes
333system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads
334system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes
335system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads
336system.cpu.misc_regfile_writes 832136 # number of misc regfile writes
337system.cpu.icache.replacements 2645 # number of replacements
338system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use
339system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks.
340system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks.
341system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks.
342system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
343system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor
344system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy
345system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy
346system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits
347system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits
348system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits
349system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits
350system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits
351system.cpu.icache.overall_hits::total 37836261 # number of overall hits
352system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses
353system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses
354system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses
355system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses
356system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses
357system.cpu.icache.overall_misses::total 5199 # number of overall misses
358system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles
359system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles
360system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles
361system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles
362system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles
363system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles
364system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses
367system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses
368system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses
369system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses
370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses
373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency
374system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
| 12sim_insts 172333279 # Number of instructions simulated
13sim_ops 188686762 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 246592 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 3853 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.inst_hits 0 # ITB inst hits
24system.cpu.dtb.inst_misses 0 # ITB inst misses
25system.cpu.dtb.read_hits 0 # DTB read hits
26system.cpu.dtb.read_misses 0 # DTB read misses
27system.cpu.dtb.write_hits 0 # DTB write hits
28system.cpu.dtb.write_misses 0 # DTB write misses
29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
38system.cpu.dtb.read_accesses 0 # DTB read accesses
39system.cpu.dtb.write_accesses 0 # DTB write accesses
40system.cpu.dtb.inst_accesses 0 # ITB inst accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.inst_hits 0 # ITB inst hits
45system.cpu.itb.inst_misses 0 # ITB inst misses
46system.cpu.itb.read_hits 0 # DTB read hits
47system.cpu.itb.read_misses 0 # DTB read misses
48system.cpu.itb.write_hits 0 # DTB write hits
49system.cpu.itb.write_misses 0 # DTB write misses
50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.itb.read_accesses 0 # DTB read accesses
60system.cpu.itb.write_accesses 0 # DTB write accesses
61system.cpu.itb.inst_accesses 0 # ITB inst accesses
62system.cpu.itb.hits 0 # DTB hits
63system.cpu.itb.misses 0 # DTB misses
64system.cpu.itb.accesses 0 # DTB accesses
65system.cpu.workload.num_syscalls 400 # Number of system calls
66system.cpu.numCycles 152645530 # number of cpu cycles simulated
67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
69system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups
70system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted
71system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect
72system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups
73system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits
74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
75system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target.
76system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions.
77system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss
78system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed
79system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered
80system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken
81system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked
82system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing
83system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked
84system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
85system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps
86system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
87system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched
88system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed
89system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total)
98system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total)
101system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
105system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total)
106system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle
107system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle
108system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle
109system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked
110system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running
111system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking
112system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing
113system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch
114system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction
115system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode
116system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode
117system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing
118system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle
119system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking
120system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst
121system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running
122system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking
123system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename
124system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
125system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full
126system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full
127system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed
128system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made
129system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups
130system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups
131system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed
132system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing
133system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed
134system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed
135system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer
136system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit.
137system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit.
138system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads.
139system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores.
140system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec)
141system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ
142system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued
143system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued
144system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling
145system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph
146system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed
147system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle
148system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle
155system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle
158system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle
159system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle
160system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
161system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
162system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
163system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle
164system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
165system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available
166system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available
167system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available
168system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available
169system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available
170system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available
171system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available
172system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available
173system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
174system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available
189system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available
190system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available
191system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available
192system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available
193system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available
194system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available
195system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available
196system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
197system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
198system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
199system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued
200system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued
201system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
202system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
203system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
204system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued
205system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued
206system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued
207system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued
208system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued
223system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued
224system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued
225system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued
226system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued
227system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued
228system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued
229system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued
230system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
231system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
232system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued
233system.cpu.iq.rate 1.659274 # Inst issue rate
234system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested
235system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst)
236system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads
237system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes
238system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses
239system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads
240system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes
241system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses
242system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses
243system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses
244system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores
245system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
246system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed
247system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed
248system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations
249system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed
250system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
251system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
252system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled
253system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
254system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
255system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing
256system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking
257system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking
258system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ
259system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch
260system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions
261system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions
262system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions
263system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall
264system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall
265system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations
266system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly
267system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly
268system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute
269system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions
270system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed
271system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute
272system.cpu.iew.exec_swp 0 # number of swp insts executed
273system.cpu.iew.exec_nop 58893 # number of nop insts executed
274system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed
275system.cpu.iew.exec_branches 54101167 # Number of branches executed
276system.cpu.iew.exec_stores 13816344 # Number of stores executed
277system.cpu.iew.exec_rate 1.612486 # Inst execution rate
278system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit
279system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back
280system.cpu.iew.wb_producers 150184249 # num instructions producing a value
281system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value
282system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
283system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle
284system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back
285system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
286system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions
287system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions
288system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit
289system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards
290system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted
291system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle
292system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle
299system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle
302system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle
303system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle
304system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
305system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
306system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
307system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle
308system.cpu.commit.committedInsts 172347667 # Number of instructions committed
309system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed
310system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
311system.cpu.commit.refs 42506219 # Number of memory references committed
312system.cpu.commit.loads 29855535 # Number of loads committed
313system.cpu.commit.membars 22408 # Number of memory barriers committed
314system.cpu.commit.branches 40287733 # Number of branches committed
315system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
316system.cpu.commit.int_insts 150130425 # Number of committed integer instructions.
317system.cpu.commit.function_calls 1848934 # Number of function calls committed.
318system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached
319system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
320system.cpu.rob.rob_reads 458778355 # The number of ROB reads
321system.cpu.rob.rob_writes 693498788 # The number of ROB writes
322system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself
323system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling
324system.cpu.committedInsts 172333279 # Number of Instructions Simulated
325system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated
326system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated
327system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction
328system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads
329system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle
330system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads
331system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads
332system.cpu.int_regfile_writes 388952433 # number of integer regfile writes
333system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads
334system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes
335system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads
336system.cpu.misc_regfile_writes 832136 # number of misc regfile writes
337system.cpu.icache.replacements 2645 # number of replacements
338system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use
339system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks.
340system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks.
341system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks.
342system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
343system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor
344system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy
345system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy
346system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits
347system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits
348system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits
349system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits
350system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits
351system.cpu.icache.overall_hits::total 37836261 # number of overall hits
352system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses
353system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses
354system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses
355system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses
356system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses
357system.cpu.icache.overall_misses::total 5199 # number of overall misses
358system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles
359system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles
360system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles
361system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles
362system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles
363system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles
364system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses)
366system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses
367system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses
368system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses
369system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses
370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses
373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency
374system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
380system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
381system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 380system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
381system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
382system.cpu.icache.fast_writes 0 # number of fast writes performed
383system.cpu.icache.cache_copies 0 # number of cache copies performed
384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits
385system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits
386system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits
387system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits
388system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits
389system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits
390system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses
391system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses
392system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses
393system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses
394system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses
395system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses
396system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles
397system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles
402system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses
403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses
404system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses
405system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency
406system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
407system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
408system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu.dcache.replacements 59 # number of replacements
410system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use
411system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks.
412system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks.
413system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks.
414system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor
416system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy
417system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy
418system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits
419system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits
420system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits
421system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits
422system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits
423system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits
424system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits
425system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits
426system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits
427system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits
428system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits
429system.cpu.dcache.overall_hits::total 47275886 # number of overall hits
430system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses
431system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses
432system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses
433system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses
434system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
435system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
436system.cpu.dcache.demand_misses::cpu.data 9470 # number of demand (read+write) misses
437system.cpu.dcache.demand_misses::total 9470 # number of demand (read+write) misses
438system.cpu.dcache.overall_misses::cpu.data 9470 # number of overall misses
439system.cpu.dcache.overall_misses::total 9470 # number of overall misses
440system.cpu.dcache.ReadReq_miss_latency::cpu.data 60591000 # number of ReadReq miss cycles
441system.cpu.dcache.ReadReq_miss_latency::total 60591000 # number of ReadReq miss cycles
442system.cpu.dcache.WriteReq_miss_latency::cpu.data 237329500 # number of WriteReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::total 237329500 # number of WriteReq miss cycles
444system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles
445system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles
446system.cpu.dcache.demand_miss_latency::cpu.data 297920500 # number of demand (read+write) miss cycles
447system.cpu.dcache.demand_miss_latency::total 297920500 # number of demand (read+write) miss cycles
448system.cpu.dcache.overall_miss_latency::cpu.data 297920500 # number of overall miss cycles
449system.cpu.dcache.overall_miss_latency::total 297920500 # number of overall miss cycles
450system.cpu.dcache.ReadReq_accesses::cpu.data 34921069 # number of ReadReq accesses(hits+misses)
451system.cpu.dcache.ReadReq_accesses::total 34921069 # number of ReadReq accesses(hits+misses)
452system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
453system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
454system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses)
455system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses)
456system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses
459system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses
460system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses
461system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses
462system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
463system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses
464system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses
465system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses
466system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses
467system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency
468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency
469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency
470system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
473system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
| 382system.cpu.icache.fast_writes 0 # number of fast writes performed
383system.cpu.icache.cache_copies 0 # number of cache copies performed
384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits
385system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits
386system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits
387system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits
388system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits
389system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits
390system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses
391system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses
392system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses
393system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses
394system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses
395system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses
396system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles
397system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles
402system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses
403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses
404system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses
405system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency
406system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
407system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
408system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
409system.cpu.dcache.replacements 59 # number of replacements
410system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use
411system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks.
412system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks.
413system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks.
414system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor
416system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy
417system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy
418system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits
419system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits
420system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits
421system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits
422system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits
423system.cpu.dcache.LoadLockedReq_hits::total 30319 # number of LoadLockedReq hits
424system.cpu.dcache.StoreCondReq_hits::cpu.data 28457 # number of StoreCondReq hits
425system.cpu.dcache.StoreCondReq_hits::total 28457 # number of StoreCondReq hits
426system.cpu.dcache.demand_hits::cpu.data 47275886 # number of demand (read+write) hits
427system.cpu.dcache.demand_hits::total 47275886 # number of demand (read+write) hits
428system.cpu.dcache.overall_hits::cpu.data 47275886 # number of overall hits
429system.cpu.dcache.overall_hits::total 47275886 # number of overall hits
430system.cpu.dcache.ReadReq_misses::cpu.data 1860 # number of ReadReq misses
431system.cpu.dcache.ReadReq_misses::total 1860 # number of ReadReq misses
432system.cpu.dcache.WriteReq_misses::cpu.data 7610 # number of WriteReq misses
433system.cpu.dcache.WriteReq_misses::total 7610 # number of WriteReq misses
434system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
435system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
436system.cpu.dcache.demand_misses::cpu.data 9470 # number of demand (read+write) misses
437system.cpu.dcache.demand_misses::total 9470 # number of demand (read+write) misses
438system.cpu.dcache.overall_misses::cpu.data 9470 # number of overall misses
439system.cpu.dcache.overall_misses::total 9470 # number of overall misses
440system.cpu.dcache.ReadReq_miss_latency::cpu.data 60591000 # number of ReadReq miss cycles
441system.cpu.dcache.ReadReq_miss_latency::total 60591000 # number of ReadReq miss cycles
442system.cpu.dcache.WriteReq_miss_latency::cpu.data 237329500 # number of WriteReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::total 237329500 # number of WriteReq miss cycles
444system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles
445system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles
446system.cpu.dcache.demand_miss_latency::cpu.data 297920500 # number of demand (read+write) miss cycles
447system.cpu.dcache.demand_miss_latency::total 297920500 # number of demand (read+write) miss cycles
448system.cpu.dcache.overall_miss_latency::cpu.data 297920500 # number of overall miss cycles
449system.cpu.dcache.overall_miss_latency::total 297920500 # number of overall miss cycles
450system.cpu.dcache.ReadReq_accesses::cpu.data 34921069 # number of ReadReq accesses(hits+misses)
451system.cpu.dcache.ReadReq_accesses::total 34921069 # number of ReadReq accesses(hits+misses)
452system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
453system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
454system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses)
455system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses)
456system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses)
457system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses)
458system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses
459system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses
460system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses
461system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses
462system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
463system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses
464system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses
465system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses
466system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses
467system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency
468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency
469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency
470system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
473system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
476system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
| 476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
477system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked
478system.cpu.dcache.fast_writes 0 # number of fast writes performed
479system.cpu.dcache.cache_copies 0 # number of cache copies performed
480system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
481system.cpu.dcache.writebacks::total 18 # number of writebacks
482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits
483system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits
484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits
485system.cpu.dcache.WriteReq_mshr_hits::total 6533 # number of WriteReq MSHR hits
486system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
487system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
488system.cpu.dcache.demand_mshr_hits::cpu.data 7589 # number of demand (read+write) MSHR hits
489system.cpu.dcache.demand_mshr_hits::total 7589 # number of demand (read+write) MSHR hits
490system.cpu.dcache.overall_mshr_hits::cpu.data 7589 # number of overall MSHR hits
491system.cpu.dcache.overall_mshr_hits::total 7589 # number of overall MSHR hits
492system.cpu.dcache.ReadReq_mshr_misses::cpu.data 804 # number of ReadReq MSHR misses
493system.cpu.dcache.ReadReq_mshr_misses::total 804 # number of ReadReq MSHR misses
494system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
495system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
496system.cpu.dcache.demand_mshr_misses::cpu.data 1881 # number of demand (read+write) MSHR misses
497system.cpu.dcache.demand_mshr_misses::total 1881 # number of demand (read+write) MSHR misses
498system.cpu.dcache.overall_mshr_misses::cpu.data 1881 # number of overall MSHR misses
499system.cpu.dcache.overall_mshr_misses::total 1881 # number of overall MSHR misses
500system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25610500 # number of ReadReq MSHR miss cycles
501system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles
502system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles
508system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
509system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
510system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency
513system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency
514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
515system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
516system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
517system.cpu.l2cache.replacements 0 # number of replacements
518system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use
519system.cpu.l2cache.total_refs 2396 # Total number of references to valid blocks.
520system.cpu.l2cache.sampled_refs 2793 # Sample count of references to valid blocks.
521system.cpu.l2cache.avg_refs 0.857859 # Average number of references to valid blocks.
522system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
523system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor
524system.cpu.l2cache.occ_blocks::cpu.inst 1457.512395 # Average occupied blocks per requestor
525system.cpu.l2cache.occ_blocks::cpu.data 556.224996 # Average occupied blocks per requestor
526system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy
527system.cpu.l2cache.occ_percent::cpu.inst 0.044480 # Average percentage of cache occupancy
528system.cpu.l2cache.occ_percent::cpu.data 0.016975 # Average percentage of cache occupancy
529system.cpu.l2cache.occ_percent::total 0.061577 # Average percentage of cache occupancy
530system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits
531system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits
532system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits
533system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
534system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
535system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits
536system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits
537system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits
538system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
539system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits
540system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits
541system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
542system.cpu.l2cache.overall_hits::total 2405 # number of overall hits
543system.cpu.l2cache.ReadReq_misses::cpu.inst 2087 # number of ReadReq misses
544system.cpu.l2cache.ReadReq_misses::cpu.data 716 # number of ReadReq misses
545system.cpu.l2cache.ReadReq_misses::total 2803 # number of ReadReq misses
546system.cpu.l2cache.ReadExReq_misses::cpu.data 1068 # number of ReadExReq misses
547system.cpu.l2cache.ReadExReq_misses::total 1068 # number of ReadExReq misses
548system.cpu.l2cache.demand_misses::cpu.inst 2087 # number of demand (read+write) misses
549system.cpu.l2cache.demand_misses::cpu.data 1784 # number of demand (read+write) misses
550system.cpu.l2cache.demand_misses::total 3871 # number of demand (read+write) misses
551system.cpu.l2cache.overall_misses::cpu.inst 2087 # number of overall misses
552system.cpu.l2cache.overall_misses::cpu.data 1784 # number of overall misses
553system.cpu.l2cache.overall_misses::total 3871 # number of overall misses
554system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71492500 # number of ReadReq miss cycles
555system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24574000 # number of ReadReq miss cycles
556system.cpu.l2cache.ReadReq_miss_latency::total 96066500 # number of ReadReq miss cycles
557system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36706000 # number of ReadExReq miss cycles
558system.cpu.l2cache.ReadExReq_miss_latency::total 36706000 # number of ReadExReq miss cycles
559system.cpu.l2cache.demand_miss_latency::cpu.inst 71492500 # number of demand (read+write) miss cycles
560system.cpu.l2cache.demand_miss_latency::cpu.data 61280000 # number of demand (read+write) miss cycles
561system.cpu.l2cache.demand_miss_latency::total 132772500 # number of demand (read+write) miss cycles
562system.cpu.l2cache.overall_miss_latency::cpu.inst 71492500 # number of overall miss cycles
563system.cpu.l2cache.overall_miss_latency::cpu.data 61280000 # number of overall miss cycles
564system.cpu.l2cache.overall_miss_latency::total 132772500 # number of overall miss cycles
565system.cpu.l2cache.ReadReq_accesses::cpu.inst 4395 # number of ReadReq accesses(hits+misses)
566system.cpu.l2cache.ReadReq_accesses::cpu.data 804 # number of ReadReq accesses(hits+misses)
567system.cpu.l2cache.ReadReq_accesses::total 5199 # number of ReadReq accesses(hits+misses)
568system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
569system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
570system.cpu.l2cache.ReadExReq_accesses::cpu.data 1077 # number of ReadExReq accesses(hits+misses)
571system.cpu.l2cache.ReadExReq_accesses::total 1077 # number of ReadExReq accesses(hits+misses)
572system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses
573system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses
574system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses
575system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses
576system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses
577system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses
578system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses
579system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses
580system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses
581system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses
582system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses
583system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses
584system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses
585system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency
586system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency
587system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency
588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
590system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
591system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
592system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
593system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
594system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
| 477system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked
478system.cpu.dcache.fast_writes 0 # number of fast writes performed
479system.cpu.dcache.cache_copies 0 # number of cache copies performed
480system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
481system.cpu.dcache.writebacks::total 18 # number of writebacks
482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits
483system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits
484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits
485system.cpu.dcache.WriteReq_mshr_hits::total 6533 # number of WriteReq MSHR hits
486system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
487system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
488system.cpu.dcache.demand_mshr_hits::cpu.data 7589 # number of demand (read+write) MSHR hits
489system.cpu.dcache.demand_mshr_hits::total 7589 # number of demand (read+write) MSHR hits
490system.cpu.dcache.overall_mshr_hits::cpu.data 7589 # number of overall MSHR hits
491system.cpu.dcache.overall_mshr_hits::total 7589 # number of overall MSHR hits
492system.cpu.dcache.ReadReq_mshr_misses::cpu.data 804 # number of ReadReq MSHR misses
493system.cpu.dcache.ReadReq_mshr_misses::total 804 # number of ReadReq MSHR misses
494system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
495system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
496system.cpu.dcache.demand_mshr_misses::cpu.data 1881 # number of demand (read+write) MSHR misses
497system.cpu.dcache.demand_mshr_misses::total 1881 # number of demand (read+write) MSHR misses
498system.cpu.dcache.overall_mshr_misses::cpu.data 1881 # number of overall MSHR misses
499system.cpu.dcache.overall_mshr_misses::total 1881 # number of overall MSHR misses
500system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25610500 # number of ReadReq MSHR miss cycles
501system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles
502system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles
503system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles
504system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles
505system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles
506system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles
507system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles
508system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
509system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
510system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency
513system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency
514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
515system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
516system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
517system.cpu.l2cache.replacements 0 # number of replacements
518system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use
519system.cpu.l2cache.total_refs 2396 # Total number of references to valid blocks.
520system.cpu.l2cache.sampled_refs 2793 # Sample count of references to valid blocks.
521system.cpu.l2cache.avg_refs 0.857859 # Average number of references to valid blocks.
522system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
523system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor
524system.cpu.l2cache.occ_blocks::cpu.inst 1457.512395 # Average occupied blocks per requestor
525system.cpu.l2cache.occ_blocks::cpu.data 556.224996 # Average occupied blocks per requestor
526system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy
527system.cpu.l2cache.occ_percent::cpu.inst 0.044480 # Average percentage of cache occupancy
528system.cpu.l2cache.occ_percent::cpu.data 0.016975 # Average percentage of cache occupancy
529system.cpu.l2cache.occ_percent::total 0.061577 # Average percentage of cache occupancy
530system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits
531system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits
532system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits
533system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
534system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
535system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits
536system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits
537system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits
538system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
539system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits
540system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits
541system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
542system.cpu.l2cache.overall_hits::total 2405 # number of overall hits
543system.cpu.l2cache.ReadReq_misses::cpu.inst 2087 # number of ReadReq misses
544system.cpu.l2cache.ReadReq_misses::cpu.data 716 # number of ReadReq misses
545system.cpu.l2cache.ReadReq_misses::total 2803 # number of ReadReq misses
546system.cpu.l2cache.ReadExReq_misses::cpu.data 1068 # number of ReadExReq misses
547system.cpu.l2cache.ReadExReq_misses::total 1068 # number of ReadExReq misses
548system.cpu.l2cache.demand_misses::cpu.inst 2087 # number of demand (read+write) misses
549system.cpu.l2cache.demand_misses::cpu.data 1784 # number of demand (read+write) misses
550system.cpu.l2cache.demand_misses::total 3871 # number of demand (read+write) misses
551system.cpu.l2cache.overall_misses::cpu.inst 2087 # number of overall misses
552system.cpu.l2cache.overall_misses::cpu.data 1784 # number of overall misses
553system.cpu.l2cache.overall_misses::total 3871 # number of overall misses
554system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71492500 # number of ReadReq miss cycles
555system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24574000 # number of ReadReq miss cycles
556system.cpu.l2cache.ReadReq_miss_latency::total 96066500 # number of ReadReq miss cycles
557system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36706000 # number of ReadExReq miss cycles
558system.cpu.l2cache.ReadExReq_miss_latency::total 36706000 # number of ReadExReq miss cycles
559system.cpu.l2cache.demand_miss_latency::cpu.inst 71492500 # number of demand (read+write) miss cycles
560system.cpu.l2cache.demand_miss_latency::cpu.data 61280000 # number of demand (read+write) miss cycles
561system.cpu.l2cache.demand_miss_latency::total 132772500 # number of demand (read+write) miss cycles
562system.cpu.l2cache.overall_miss_latency::cpu.inst 71492500 # number of overall miss cycles
563system.cpu.l2cache.overall_miss_latency::cpu.data 61280000 # number of overall miss cycles
564system.cpu.l2cache.overall_miss_latency::total 132772500 # number of overall miss cycles
565system.cpu.l2cache.ReadReq_accesses::cpu.inst 4395 # number of ReadReq accesses(hits+misses)
566system.cpu.l2cache.ReadReq_accesses::cpu.data 804 # number of ReadReq accesses(hits+misses)
567system.cpu.l2cache.ReadReq_accesses::total 5199 # number of ReadReq accesses(hits+misses)
568system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
569system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
570system.cpu.l2cache.ReadExReq_accesses::cpu.data 1077 # number of ReadExReq accesses(hits+misses)
571system.cpu.l2cache.ReadExReq_accesses::total 1077 # number of ReadExReq accesses(hits+misses)
572system.cpu.l2cache.demand_accesses::cpu.inst 4395 # number of demand (read+write) accesses
573system.cpu.l2cache.demand_accesses::cpu.data 1881 # number of demand (read+write) accesses
574system.cpu.l2cache.demand_accesses::total 6276 # number of demand (read+write) accesses
575system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses
576system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses
577system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses
578system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses
579system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses
580system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses
581system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses
582system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses
583system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses
584system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses
585system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency
586system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency
587system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency
588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
590system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
591system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
592system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
593system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
594system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
596system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
597system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 596system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
597system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
598system.cpu.l2cache.fast_writes 0 # number of fast writes performed
599system.cpu.l2cache.cache_copies 0 # number of cache copies performed
600system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
601system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
602system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
603system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
604system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
605system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
606system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
607system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
608system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits
609system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses
610system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses
611system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses
612system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses
613system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses
614system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses
615system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses
616system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses
617system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses
618system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses
619system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses
620system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles
621system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles
622system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles
623system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles
624system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles
625system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles
626system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles
627system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles
628system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles
629system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles
630system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles
631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses
632system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses
633system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses
634system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses
635system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses
636system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses
637system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses
638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency
639system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency
640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency
641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
645system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
646
647---------- End Simulation Statistics ----------
| 598system.cpu.l2cache.fast_writes 0 # number of fast writes performed
599system.cpu.l2cache.cache_copies 0 # number of cache copies performed
600system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
601system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
602system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
603system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
604system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
605system.cpu.l2cache.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
606system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
607system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
608system.cpu.l2cache.overall_mshr_hits::total 18 # number of overall MSHR hits
609system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2084 # number of ReadReq MSHR misses
610system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 701 # number of ReadReq MSHR misses
611system.cpu.l2cache.ReadReq_mshr_misses::total 2785 # number of ReadReq MSHR misses
612system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1068 # number of ReadExReq MSHR misses
613system.cpu.l2cache.ReadExReq_mshr_misses::total 1068 # number of ReadExReq MSHR misses
614system.cpu.l2cache.demand_mshr_misses::cpu.inst 2084 # number of demand (read+write) MSHR misses
615system.cpu.l2cache.demand_mshr_misses::cpu.data 1769 # number of demand (read+write) MSHR misses
616system.cpu.l2cache.demand_mshr_misses::total 3853 # number of demand (read+write) MSHR misses
617system.cpu.l2cache.overall_mshr_misses::cpu.inst 2084 # number of overall MSHR misses
618system.cpu.l2cache.overall_mshr_misses::cpu.data 1769 # number of overall MSHR misses
619system.cpu.l2cache.overall_mshr_misses::total 3853 # number of overall MSHR misses
620system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64692000 # number of ReadReq MSHR miss cycles
621system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21857000 # number of ReadReq MSHR miss cycles
622system.cpu.l2cache.ReadReq_mshr_miss_latency::total 86549000 # number of ReadReq MSHR miss cycles
623system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33156000 # number of ReadExReq MSHR miss cycles
624system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33156000 # number of ReadExReq MSHR miss cycles
625system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64692000 # number of demand (read+write) MSHR miss cycles
626system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 55013000 # number of demand (read+write) MSHR miss cycles
627system.cpu.l2cache.demand_mshr_miss_latency::total 119705000 # number of demand (read+write) MSHR miss cycles
628system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles
629system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles
630system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles
631system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses
632system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses
633system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses
634system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses
635system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses
636system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses
637system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses
638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency
639system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency
640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency
641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
645system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
646
647---------- End Simulation Statistics ----------
|