12sim_insts 172303022 # Number of instructions simulated
13sim_ops 181635954 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory
19system.physmem.bytes_read::total 789952 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory
26system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.readReqs 12344 # Number of read requests accepted
37system.physmem.writeReqs 0 # Number of write requests accepted
38system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue
39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
40system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM
41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
43system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side
44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
48system.physmem.perBankRdBursts::0 1112 # Per bank write bursts
49system.physmem.perBankRdBursts::1 371 # Per bank write bursts
50system.physmem.perBankRdBursts::2 5091 # Per bank write bursts
51system.physmem.perBankRdBursts::3 435 # Per bank write bursts
52system.physmem.perBankRdBursts::4 1954 # Per bank write bursts
53system.physmem.perBankRdBursts::5 426 # Per bank write bursts
54system.physmem.perBankRdBursts::6 266 # Per bank write bursts
55system.physmem.perBankRdBursts::7 369 # Per bank write bursts
56system.physmem.perBankRdBursts::8 265 # Per bank write bursts
57system.physmem.perBankRdBursts::9 221 # Per bank write bursts
58system.physmem.perBankRdBursts::10 295 # Per bank write bursts
59system.physmem.perBankRdBursts::11 323 # Per bank write bursts
60system.physmem.perBankRdBursts::12 197 # Per bank write bursts
61system.physmem.perBankRdBursts::13 249 # Per bank write bursts
62system.physmem.perBankRdBursts::14 227 # Per bank write bursts
63system.physmem.perBankRdBursts::15 543 # Per bank write bursts
64system.physmem.perBankWrBursts::0 0 # Per bank write bursts
65system.physmem.perBankWrBursts::1 0 # Per bank write bursts
66system.physmem.perBankWrBursts::2 0 # Per bank write bursts
67system.physmem.perBankWrBursts::3 0 # Per bank write bursts
68system.physmem.perBankWrBursts::4 0 # Per bank write bursts
69system.physmem.perBankWrBursts::5 0 # Per bank write bursts
70system.physmem.perBankWrBursts::6 0 # Per bank write bursts
71system.physmem.perBankWrBursts::7 0 # Per bank write bursts
72system.physmem.perBankWrBursts::8 0 # Per bank write bursts
73system.physmem.perBankWrBursts::9 0 # Per bank write bursts
74system.physmem.perBankWrBursts::10 0 # Per bank write bursts
75system.physmem.perBankWrBursts::11 0 # Per bank write bursts
76system.physmem.perBankWrBursts::12 0 # Per bank write bursts
77system.physmem.perBankWrBursts::13 0 # Per bank write bursts
78system.physmem.perBankWrBursts::14 0 # Per bank write bursts
79system.physmem.perBankWrBursts::15 0 # Per bank write bursts
80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
82system.physmem.totGap 85490422000 # Total gap between requests
83system.physmem.readPktSize::0 0 # Read request sizes (log2)
84system.physmem.readPktSize::1 0 # Read request sizes (log2)
85system.physmem.readPktSize::2 0 # Read request sizes (log2)
86system.physmem.readPktSize::3 0 # Read request sizes (log2)
87system.physmem.readPktSize::4 0 # Read request sizes (log2)
88system.physmem.readPktSize::5 0 # Read request sizes (log2)
89system.physmem.readPktSize::6 12344 # Read request sizes (log2)
90system.physmem.writePktSize::0 0 # Write request sizes (log2)
91system.physmem.writePktSize::1 0 # Write request sizes (log2)
92system.physmem.writePktSize::2 0 # Write request sizes (log2)
93system.physmem.writePktSize::3 0 # Write request sizes (log2)
94system.physmem.writePktSize::4 0 # Write request sizes (log2)
95system.physmem.writePktSize::5 0 # Write request sizes (log2)
96system.physmem.writePktSize::6 0 # Write request sizes (log2)
97system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
193system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation
207system.physmem.totQLat 167084529 # Total ticks spent queuing
208system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM
209system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers
210system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst
211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
212system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst
213system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s
214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
215system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s
216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
218system.physmem.busUtil 0.07 # Data bus utilization in percentage
219system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads
220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
221system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
223system.physmem.readRowHits 5095 # Number of row buffer hits during reads
224system.physmem.writeRowHits 0 # Number of row buffer hits during writes
225system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads
226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
227system.physmem.avgGap 6925666.07 # Average gap between requests
228system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined
229system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ)
230system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ)
231system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ)
232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
233system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ)
234system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ)
235system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ)
236system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ)
237system.physmem_0.averagePower 691.542258 # Core power per rank (mW)
238system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states
239system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states
240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
241system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states
242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
243system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ)
244system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ)
245system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ)
246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
247system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ)
248system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ)
249system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ)
250system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ)
251system.physmem_1.averagePower 670.413332 # Core power per rank (mW)
252system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states
253system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states
254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
255system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states
256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
257system.cpu.branchPred.lookups 85927149 # Number of BP lookups
258system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted
259system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect
260system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups
261system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits
262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
263system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage
264system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target.
265system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions.
266system.cpu_clk_domain.clock 500 # Clock period in ticks
267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
285system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
286system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
287system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
296system.cpu.dtb.walker.walks 0 # Table walker walks requested
297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.inst_hits 0 # ITB inst hits
305system.cpu.dtb.inst_misses 0 # ITB inst misses
306system.cpu.dtb.read_hits 0 # DTB read hits
307system.cpu.dtb.read_misses 0 # DTB read misses
308system.cpu.dtb.write_hits 0 # DTB write hits
309system.cpu.dtb.write_misses 0 # DTB write misses
310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dtb.read_accesses 0 # DTB read accesses
320system.cpu.dtb.write_accesses 0 # DTB write accesses
321system.cpu.dtb.inst_accesses 0 # ITB inst accesses
322system.cpu.dtb.hits 0 # DTB hits
323system.cpu.dtb.misses 0 # DTB misses
324system.cpu.dtb.accesses 0 # DTB accesses
325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
354system.cpu.itb.walker.walks 0 # Table walker walks requested
355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.inst_hits 0 # ITB inst hits
363system.cpu.itb.inst_misses 0 # ITB inst misses
364system.cpu.itb.read_hits 0 # DTB read hits
365system.cpu.itb.read_misses 0 # DTB read misses
366system.cpu.itb.write_hits 0 # DTB write hits
367system.cpu.itb.write_misses 0 # DTB write misses
368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
370system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
371system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
372system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
373system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
374system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
375system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.itb.read_accesses 0 # DTB read accesses
378system.cpu.itb.write_accesses 0 # DTB write accesses
379system.cpu.itb.inst_accesses 0 # ITB inst accesses
380system.cpu.itb.hits 0 # DTB hits
381system.cpu.itb.misses 0 # DTB misses
382system.cpu.itb.accesses 0 # DTB accesses
383system.cpu.workload.num_syscalls 400 # Number of system calls
384system.cpu.numCycles 170980863 # number of cpu cycles simulated
385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
387system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss
388system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed
389system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered
390system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken
391system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked
392system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing
393system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
394system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions
395system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR
396system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched
397system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed
398system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle
411system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle
412system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle
413system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked
414system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running
415system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking
416system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing
417system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch
418system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction
419system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode
420system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode
421system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing
422system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle
423system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking
424system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst
425system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running
426system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking
427system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename
428system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename
429system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full
430system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full
431system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full
432system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full
433system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers
434system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed
435system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made
436system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups
437system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups
438system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
439system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing
440system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed
441system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed
442system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer
443system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit.
444system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit.
445system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads.
446system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores.
447system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec)
448system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ
449system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued
450system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued
451system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling
452system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph
453system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed
454system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
470system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle
471system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
472system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available
473system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available
474system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available
475system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available
476system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available
477system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available
478system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available
479system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available
480system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available
500system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available
501system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available
502system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available
503system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
504system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
505system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
506system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued
507system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued
508system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
509system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
510system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
511system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
512system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
513system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
514system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued
535system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued
536system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued
537system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
538system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
539system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued
540system.cpu.iq.rate 1.256951 # Inst issue rate
541system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested
542system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst)
543system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads
544system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes
545system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses
546system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads
547system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes
548system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses
549system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses
550system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses
551system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores
552system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
553system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed
554system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed
555system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations
556system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed
557system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
558system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
559system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled
560system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked
561system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
562system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing
563system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking
564system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking
565system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ
566system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
567system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions
568system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions
569system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions
570system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall
571system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall
572system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations
573system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly
574system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly
575system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute
576system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions
577system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed
578system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute
579system.cpu.iew.exec_swp 0 # number of swp insts executed
580system.cpu.iew.exec_nop 15961 # number of nop insts executed
581system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed
582system.cpu.iew.exec_branches 44936158 # Number of branches executed
583system.cpu.iew.exec_stores 13139841 # Number of stores executed
584system.cpu.iew.exec_rate 1.213760 # Inst execution rate
585system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit
586system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back
587system.cpu.iew.wb_producers 129474820 # num instructions producing a value
588system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value
589system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle
590system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back
591system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit
592system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
593system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted
594system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle
595system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle
611system.cpu.commit.committedInsts 172317410 # Number of instructions committed
612system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
613system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
614system.cpu.commit.refs 40540778 # Number of memory references committed
615system.cpu.commit.loads 27896144 # Number of loads committed
616system.cpu.commit.membars 22408 # Number of memory barriers committed
617system.cpu.commit.branches 40300312 # Number of branches committed
618system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
619system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
620system.cpu.commit.function_calls 1848934 # Number of function calls committed.
621system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
622system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction
623system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
624system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
625system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
626system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
627system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
628system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
629system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
630system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
631system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
632system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
633system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
634system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
635system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
636system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
637system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
638system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
639system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
640system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
641system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
642system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
643system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
644system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
645system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
646system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
647system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
648system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
649system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
650system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
651system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
652system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
653system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
654system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
655system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction
656system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached
657system.cpu.rob.rob_reads 406631126 # The number of ROB reads
658system.cpu.rob.rob_writes 513844376 # The number of ROB writes
659system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself
660system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling
661system.cpu.committedInsts 172303022 # Number of Instructions Simulated
662system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated
663system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction
664system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads
665system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle
666system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads
667system.cpu.int_regfile_reads 218966975 # number of integer regfile reads
668system.cpu.int_regfile_writes 114516229 # number of integer regfile writes
669system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads
670system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes
671system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads
672system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes
673system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads
674system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
675system.cpu.dcache.tags.replacements 72854 # number of replacements
676system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use
677system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks.
678system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks.
679system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks.
680system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit.
681system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor
682system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy
683system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy
684system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
685system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
686system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
687system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id
688system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
689system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
690system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
691system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses
692system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses
693system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits
694system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits
695system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits
696system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits
697system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits
698system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits
699system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits
700system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits
701system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
702system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
703system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits
704system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits
705system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits
706system.cpu.dcache.overall_hits::total 41069884 # number of overall hits
707system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses
708system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses
709system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses
710system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses
711system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses
712system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses
713system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses
714system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses
715system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses
716system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses
717system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses
718system.cpu.dcache.overall_misses::total 112572 # number of overall misses
719system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles
720system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles
721system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles
722system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles
723system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles
724system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles
725system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles
726system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles
727system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles
728system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles
729system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses)
730system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses)
731system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
732system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
733system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses)
734system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses)
735system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
736system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
737system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
738system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
739system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses
740system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses
741system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses
742system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses
743system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses
744system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses
745system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses
746system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses
747system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses
748system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses
749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses
750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses
751system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses
752system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses
753system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses
754system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses
755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency
756system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency
757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency
758system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency
759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency
760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency
761system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency
762system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency
763system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency
764system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency
765system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked
766system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked
767system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
768system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked
769system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked
770system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked
771system.cpu.dcache.fast_writes 0 # number of fast writes performed
772system.cpu.dcache.cache_copies 0 # number of cache copies performed
773system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks
774system.cpu.dcache.writebacks::total 72854 # number of writebacks
775system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits
776system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits
777system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits
778system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits
779system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits
780system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits
781system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits
782system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits
783system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits
784system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits
785system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses
786system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses
787system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses
788system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses
789system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses
790system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses
791system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses
792system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses
793system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses
794system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses
795system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles
796system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles
797system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles
798system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles
799system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles
800system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles
801system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles
802system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles
803system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles
804system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles
805system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses
806system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses
807system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses
808system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses
809system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses
810system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses
811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses
812system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses
813system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses
814system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency
816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency
817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency
818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency
819system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency
820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency
821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency
822system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency
823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency
824system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency
825system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
826system.cpu.icache.tags.replacements 54401 # number of replacements
827system.cpu.icache.tags.tagsinuse 510.602972 # Cycle average of tags in use
828system.cpu.icache.tags.total_refs 78901806 # Total number of references to valid blocks.
829system.cpu.icache.tags.sampled_refs 54913 # Sample count of references to valid blocks.
830system.cpu.icache.tags.avg_refs 1436.851128 # Average number of references to valid blocks.
831system.cpu.icache.tags.warmup_cycle 84733597500 # Cycle when the warmup percentage was hit.
832system.cpu.icache.tags.occ_blocks::cpu.inst 510.602972 # Average occupied blocks per requestor
833system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy
834system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy
835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
836system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
837system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
838system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
839system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
840system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
842system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses
843system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses
844system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits
845system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits
846system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits
847system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits
848system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits
849system.cpu.icache.overall_hits::total 78901806 # number of overall hits
850system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses
851system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses
852system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses
853system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses
854system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses
855system.cpu.icache.overall_misses::total 58402 # number of overall misses
856system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles
857system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles
858system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles
859system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles
860system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles
861system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles
862system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses)
863system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses)
864system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses
865system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses
866system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses
867system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses
868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses
869system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses
870system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses
871system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses
872system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # miss rate for overall accesses
873system.cpu.icache.overall_miss_rate::total 0.000740 # miss rate for overall accesses
874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772 # average ReadReq miss latency
875system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772 # average ReadReq miss latency
876system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency
877system.cpu.icache.demand_avg_miss_latency::total 19811.965772 # average overall miss latency
878system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency
879system.cpu.icache.overall_avg_miss_latency::total 19811.965772 # average overall miss latency
880system.cpu.icache.blocked_cycles::no_mshrs 72401 # number of cycles access was blocked
881system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked
882system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked
883system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
884system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked
885system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked
886system.cpu.icache.fast_writes 0 # number of fast writes performed
887system.cpu.icache.cache_copies 0 # number of cache copies performed
888system.cpu.icache.writebacks::writebacks 54401 # number of writebacks
889system.cpu.icache.writebacks::total 54401 # number of writebacks
890system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits
891system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits
892system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # number of demand (read+write) MSHR hits
893system.cpu.icache.demand_mshr_hits::total 3488 # number of demand (read+write) MSHR hits
894system.cpu.icache.overall_mshr_hits::cpu.inst 3488 # number of overall MSHR hits
895system.cpu.icache.overall_mshr_hits::total 3488 # number of overall MSHR hits
896system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54914 # number of ReadReq MSHR misses
897system.cpu.icache.ReadReq_mshr_misses::total 54914 # number of ReadReq MSHR misses
898system.cpu.icache.demand_mshr_misses::cpu.inst 54914 # number of demand (read+write) MSHR misses
899system.cpu.icache.demand_mshr_misses::total 54914 # number of demand (read+write) MSHR misses
900system.cpu.icache.overall_mshr_misses::cpu.inst 54914 # number of overall MSHR misses
901system.cpu.icache.overall_mshr_misses::total 54914 # number of overall MSHR misses
902system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1043630451 # number of ReadReq MSHR miss cycles
903system.cpu.icache.ReadReq_mshr_miss_latency::total 1043630451 # number of ReadReq MSHR miss cycles
904system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1043630451 # number of demand (read+write) MSHR miss cycles
905system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles
906system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles
907system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles
908system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses
909system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses
910system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses
911system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses
912system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses
913system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses
914system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # average ReadReq mshr miss latency
915system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730 # average ReadReq mshr miss latency
916system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency
917system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency
918system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency
919system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency
920system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
921system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued
922system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified
923system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
924system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
925system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
926system.cpu.l2cache.prefetcher.pfSpanPage 1359 # number of prefetches not generated due to page crossing
927system.cpu.l2cache.tags.replacements 0 # number of replacements
928system.cpu.l2cache.tags.tagsinuse 2148.551192 # Cycle average of tags in use
929system.cpu.l2cache.tags.total_refs 159756 # Total number of references to valid blocks.
930system.cpu.l2cache.tags.sampled_refs 3199 # Sample count of references to valid blocks.
931system.cpu.l2cache.tags.avg_refs 49.939356 # Average number of references to valid blocks.
932system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
933system.cpu.l2cache.tags.occ_blocks::writebacks 1987.164357 # Average occupied blocks per requestor
934system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 161.386835 # Average occupied blocks per requestor
935system.cpu.l2cache.tags.occ_percent::writebacks 0.121287 # Average percentage of cache occupancy
936system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009850 # Average percentage of cache occupancy
937system.cpu.l2cache.tags.occ_percent::total 0.131137 # Average percentage of cache occupancy
938system.cpu.l2cache.tags.occ_task_id_blocks::1022 254 # Occupied blocks per task id
939system.cpu.l2cache.tags.occ_task_id_blocks::1024 2945 # Occupied blocks per task id
940system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
941system.cpu.l2cache.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id
942system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id
943system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
944system.cpu.l2cache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id
945system.cpu.l2cache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id
946system.cpu.l2cache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
947system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1654 # Occupied blocks per task id
948system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id
949system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179749 # Percentage of cache occupancy per task id
950system.cpu.l2cache.tags.tag_accesses 3989175 # Number of tag accesses
951system.cpu.l2cache.tags.data_accesses 3989175 # Number of data accesses
952system.cpu.l2cache.WritebackDirty_hits::writebacks 64840 # number of WritebackDirty hits
953system.cpu.l2cache.WritebackDirty_hits::total 64840 # number of WritebackDirty hits
954system.cpu.l2cache.WritebackClean_hits::writebacks 51941 # number of WritebackClean hits
955system.cpu.l2cache.WritebackClean_hits::total 51941 # number of WritebackClean hits
956system.cpu.l2cache.ReadExReq_hits::cpu.data 8403 # number of ReadExReq hits
957system.cpu.l2cache.ReadExReq_hits::total 8403 # number of ReadExReq hits
958system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 45734 # number of ReadCleanReq hits
959system.cpu.l2cache.ReadCleanReq_hits::total 45734 # number of ReadCleanReq hits
960system.cpu.l2cache.ReadSharedReq_hits::cpu.data 62891 # number of ReadSharedReq hits
961system.cpu.l2cache.ReadSharedReq_hits::total 62891 # number of ReadSharedReq hits
962system.cpu.l2cache.demand_hits::cpu.inst 45734 # number of demand (read+write) hits
963system.cpu.l2cache.demand_hits::cpu.data 71294 # number of demand (read+write) hits
964system.cpu.l2cache.demand_hits::total 117028 # number of demand (read+write) hits
965system.cpu.l2cache.overall_hits::cpu.inst 45734 # number of overall hits
966system.cpu.l2cache.overall_hits::cpu.data 71294 # number of overall hits
967system.cpu.l2cache.overall_hits::total 117028 # number of overall hits
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969system.cpu.l2cache.ReadExReq_misses::total 237 # number of ReadExReq misses
970system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9180 # number of ReadCleanReq misses
971system.cpu.l2cache.ReadCleanReq_misses::total 9180 # number of ReadCleanReq misses
972system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1835 # number of ReadSharedReq misses
973system.cpu.l2cache.ReadSharedReq_misses::total 1835 # number of ReadSharedReq misses
974system.cpu.l2cache.demand_misses::cpu.inst 9180 # number of demand (read+write) misses
975system.cpu.l2cache.demand_misses::cpu.data 2072 # number of demand (read+write) misses
976system.cpu.l2cache.demand_misses::total 11252 # number of demand (read+write) misses
977system.cpu.l2cache.overall_misses::cpu.inst 9180 # number of overall misses
978system.cpu.l2cache.overall_misses::cpu.data 2072 # number of overall misses
979system.cpu.l2cache.overall_misses::total 11252 # number of overall misses
980system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19043000 # number of ReadExReq miss cycles
981system.cpu.l2cache.ReadExReq_miss_latency::total 19043000 # number of ReadExReq miss cycles
982system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 687767000 # number of ReadCleanReq miss cycles
983system.cpu.l2cache.ReadCleanReq_miss_latency::total 687767000 # number of ReadCleanReq miss cycles
984system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 141031000 # number of ReadSharedReq miss cycles
985system.cpu.l2cache.ReadSharedReq_miss_latency::total 141031000 # number of ReadSharedReq miss cycles
986system.cpu.l2cache.demand_miss_latency::cpu.inst 687767000 # number of demand (read+write) miss cycles
987system.cpu.l2cache.demand_miss_latency::cpu.data 160074000 # number of demand (read+write) miss cycles
988system.cpu.l2cache.demand_miss_latency::total 847841000 # number of demand (read+write) miss cycles
989system.cpu.l2cache.overall_miss_latency::cpu.inst 687767000 # number of overall miss cycles
990system.cpu.l2cache.overall_miss_latency::cpu.data 160074000 # number of overall miss cycles
991system.cpu.l2cache.overall_miss_latency::total 847841000 # number of overall miss cycles
992system.cpu.l2cache.WritebackDirty_accesses::writebacks 64840 # number of WritebackDirty accesses(hits+misses)
993system.cpu.l2cache.WritebackDirty_accesses::total 64840 # number of WritebackDirty accesses(hits+misses)
994system.cpu.l2cache.WritebackClean_accesses::writebacks 51941 # number of WritebackClean accesses(hits+misses)
995system.cpu.l2cache.WritebackClean_accesses::total 51941 # number of WritebackClean accesses(hits+misses)
996system.cpu.l2cache.ReadExReq_accesses::cpu.data 8640 # number of ReadExReq accesses(hits+misses)
997system.cpu.l2cache.ReadExReq_accesses::total 8640 # number of ReadExReq accesses(hits+misses)
998system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54914 # number of ReadCleanReq accesses(hits+misses)
999system.cpu.l2cache.ReadCleanReq_accesses::total 54914 # number of ReadCleanReq accesses(hits+misses)
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1001system.cpu.l2cache.ReadSharedReq_accesses::total 64726 # number of ReadSharedReq accesses(hits+misses)
1002system.cpu.l2cache.demand_accesses::cpu.inst 54914 # number of demand (read+write) accesses
1003system.cpu.l2cache.demand_accesses::cpu.data 73366 # number of demand (read+write) accesses
1004system.cpu.l2cache.demand_accesses::total 128280 # number of demand (read+write) accesses
1005system.cpu.l2cache.overall_accesses::cpu.inst 54914 # number of overall (read+write) accesses
1006system.cpu.l2cache.overall_accesses::cpu.data 73366 # number of overall (read+write) accesses
1007system.cpu.l2cache.overall_accesses::total 128280 # number of overall (read+write) accesses
1008system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027431 # miss rate for ReadExReq accesses
1009system.cpu.l2cache.ReadExReq_miss_rate::total 0.027431 # miss rate for ReadExReq accesses
1010system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167170 # miss rate for ReadCleanReq accesses
1011system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167170 # miss rate for ReadCleanReq accesses
1012system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.028350 # miss rate for ReadSharedReq accesses
1013system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.028350 # miss rate for ReadSharedReq accesses
1014system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167170 # miss rate for demand accesses
1015system.cpu.l2cache.demand_miss_rate::cpu.data 0.028242 # miss rate for demand accesses
1016system.cpu.l2cache.demand_miss_rate::total 0.087714 # miss rate for demand accesses
1017system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167170 # miss rate for overall accesses
1018system.cpu.l2cache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses
1019system.cpu.l2cache.overall_miss_rate::total 0.087714 # miss rate for overall accesses
1020system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80350.210970 # average ReadExReq miss latency
1021system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80350.210970 # average ReadExReq miss latency
1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74920.152505 # average ReadCleanReq miss latency
1023system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74920.152505 # average ReadCleanReq miss latency
1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76856.130790 # average ReadSharedReq miss latency
1025system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76856.130790 # average ReadSharedReq miss latency
1026system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74920.152505 # average overall miss latency
1027system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77255.791506 # average overall miss latency
1028system.cpu.l2cache.demand_avg_miss_latency::total 75350.248845 # average overall miss latency
1029system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74920.152505 # average overall miss latency
1030system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77255.791506 # average overall miss latency
1031system.cpu.l2cache.overall_avg_miss_latency::total 75350.248845 # average overall miss latency
1032system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1033system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1034system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1035system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1036system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1037system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1038system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1039system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1040system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
1041system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
1042system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
1043system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
1044system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
1045system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
1046system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
1047system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
1048system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
1049system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
1050system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
1051system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
1052system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2046 # number of HardPFReq MSHR misses
1053system.cpu.l2cache.HardPFReq_mshr_misses::total 2046 # number of HardPFReq MSHR misses
1054system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses
1055system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses
1056system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9175 # number of ReadCleanReq MSHR misses
1057system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9175 # number of ReadCleanReq MSHR misses
1058system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1827 # number of ReadSharedReq MSHR misses
1059system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1827 # number of ReadSharedReq MSHR misses
1060system.cpu.l2cache.demand_mshr_misses::cpu.inst 9175 # number of demand (read+write) MSHR misses
1061system.cpu.l2cache.demand_mshr_misses::cpu.data 2063 # number of demand (read+write) MSHR misses
1062system.cpu.l2cache.demand_mshr_misses::total 11238 # number of demand (read+write) MSHR misses
1063system.cpu.l2cache.overall_mshr_misses::cpu.inst 9175 # number of overall MSHR misses
1064system.cpu.l2cache.overall_mshr_misses::cpu.data 2063 # number of overall MSHR misses
1065system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2046 # number of overall MSHR misses
1066system.cpu.l2cache.overall_mshr_misses::total 13284 # number of overall MSHR misses
1067system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of HardPFReq MSHR miss cycles
1068system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66908651 # number of HardPFReq MSHR miss cycles
1069system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17421000 # number of ReadExReq MSHR miss cycles
1070system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17421000 # number of ReadExReq MSHR miss cycles
1071system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 632417000 # number of ReadCleanReq MSHR miss cycles
1072system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 632417000 # number of ReadCleanReq MSHR miss cycles
1073system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 129587000 # number of ReadSharedReq MSHR miss cycles
1074system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 129587000 # number of ReadSharedReq MSHR miss cycles
1075system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 632417000 # number of demand (read+write) MSHR miss cycles
1076system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147008000 # number of demand (read+write) MSHR miss cycles
1077system.cpu.l2cache.demand_mshr_miss_latency::total 779425000 # number of demand (read+write) MSHR miss cycles
1078system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 632417000 # number of overall MSHR miss cycles
1079system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147008000 # number of overall MSHR miss cycles
1080system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of overall MSHR miss cycles
1081system.cpu.l2cache.overall_mshr_miss_latency::total 846333651 # number of overall MSHR miss cycles
1082system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1083system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1084system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses
1085system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses
1086system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses
1087system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses
1088system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses
1089system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses
1090system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses
1091system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses
1092system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses
1093system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses
1094system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses
1095system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1096system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses
1097system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency
1098system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency
1099system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency
1100system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency
1101system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency
1102system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency
1103system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency
1104system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency
1105system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency
1106system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency
1107system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency
1108system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency
1109system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency
1110system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency
1111system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency
1112system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1113system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter.
1114system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1115system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1116system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter.
1117system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1118system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1119system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution
1120system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution
| 12sim_insts 172303022 # Number of instructions simulated
13sim_ops 181635954 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory
19system.physmem.bytes_read::total 789952 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory
26system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.readReqs 12344 # Number of read requests accepted
37system.physmem.writeReqs 0 # Number of write requests accepted
38system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue
39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
40system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM
41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
43system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side
44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
48system.physmem.perBankRdBursts::0 1112 # Per bank write bursts
49system.physmem.perBankRdBursts::1 371 # Per bank write bursts
50system.physmem.perBankRdBursts::2 5091 # Per bank write bursts
51system.physmem.perBankRdBursts::3 435 # Per bank write bursts
52system.physmem.perBankRdBursts::4 1954 # Per bank write bursts
53system.physmem.perBankRdBursts::5 426 # Per bank write bursts
54system.physmem.perBankRdBursts::6 266 # Per bank write bursts
55system.physmem.perBankRdBursts::7 369 # Per bank write bursts
56system.physmem.perBankRdBursts::8 265 # Per bank write bursts
57system.physmem.perBankRdBursts::9 221 # Per bank write bursts
58system.physmem.perBankRdBursts::10 295 # Per bank write bursts
59system.physmem.perBankRdBursts::11 323 # Per bank write bursts
60system.physmem.perBankRdBursts::12 197 # Per bank write bursts
61system.physmem.perBankRdBursts::13 249 # Per bank write bursts
62system.physmem.perBankRdBursts::14 227 # Per bank write bursts
63system.physmem.perBankRdBursts::15 543 # Per bank write bursts
64system.physmem.perBankWrBursts::0 0 # Per bank write bursts
65system.physmem.perBankWrBursts::1 0 # Per bank write bursts
66system.physmem.perBankWrBursts::2 0 # Per bank write bursts
67system.physmem.perBankWrBursts::3 0 # Per bank write bursts
68system.physmem.perBankWrBursts::4 0 # Per bank write bursts
69system.physmem.perBankWrBursts::5 0 # Per bank write bursts
70system.physmem.perBankWrBursts::6 0 # Per bank write bursts
71system.physmem.perBankWrBursts::7 0 # Per bank write bursts
72system.physmem.perBankWrBursts::8 0 # Per bank write bursts
73system.physmem.perBankWrBursts::9 0 # Per bank write bursts
74system.physmem.perBankWrBursts::10 0 # Per bank write bursts
75system.physmem.perBankWrBursts::11 0 # Per bank write bursts
76system.physmem.perBankWrBursts::12 0 # Per bank write bursts
77system.physmem.perBankWrBursts::13 0 # Per bank write bursts
78system.physmem.perBankWrBursts::14 0 # Per bank write bursts
79system.physmem.perBankWrBursts::15 0 # Per bank write bursts
80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
82system.physmem.totGap 85490422000 # Total gap between requests
83system.physmem.readPktSize::0 0 # Read request sizes (log2)
84system.physmem.readPktSize::1 0 # Read request sizes (log2)
85system.physmem.readPktSize::2 0 # Read request sizes (log2)
86system.physmem.readPktSize::3 0 # Read request sizes (log2)
87system.physmem.readPktSize::4 0 # Read request sizes (log2)
88system.physmem.readPktSize::5 0 # Read request sizes (log2)
89system.physmem.readPktSize::6 12344 # Read request sizes (log2)
90system.physmem.writePktSize::0 0 # Write request sizes (log2)
91system.physmem.writePktSize::1 0 # Write request sizes (log2)
92system.physmem.writePktSize::2 0 # Write request sizes (log2)
93system.physmem.writePktSize::3 0 # Write request sizes (log2)
94system.physmem.writePktSize::4 0 # Write request sizes (log2)
95system.physmem.writePktSize::5 0 # Write request sizes (log2)
96system.physmem.writePktSize::6 0 # Write request sizes (log2)
97system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
193system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation
207system.physmem.totQLat 167084529 # Total ticks spent queuing
208system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM
209system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers
210system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst
211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
212system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst
213system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s
214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
215system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s
216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
218system.physmem.busUtil 0.07 # Data bus utilization in percentage
219system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads
220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
221system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
223system.physmem.readRowHits 5095 # Number of row buffer hits during reads
224system.physmem.writeRowHits 0 # Number of row buffer hits during writes
225system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads
226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
227system.physmem.avgGap 6925666.07 # Average gap between requests
228system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined
229system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ)
230system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ)
231system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ)
232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
233system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ)
234system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ)
235system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ)
236system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ)
237system.physmem_0.averagePower 691.542258 # Core power per rank (mW)
238system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states
239system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states
240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
241system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states
242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
243system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ)
244system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ)
245system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ)
246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
247system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ)
248system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ)
249system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ)
250system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ)
251system.physmem_1.averagePower 670.413332 # Core power per rank (mW)
252system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states
253system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states
254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
255system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states
256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
257system.cpu.branchPred.lookups 85927149 # Number of BP lookups
258system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted
259system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect
260system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups
261system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits
262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
263system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage
264system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target.
265system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions.
266system.cpu_clk_domain.clock 500 # Clock period in ticks
267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
285system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
286system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
287system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
296system.cpu.dtb.walker.walks 0 # Table walker walks requested
297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.inst_hits 0 # ITB inst hits
305system.cpu.dtb.inst_misses 0 # ITB inst misses
306system.cpu.dtb.read_hits 0 # DTB read hits
307system.cpu.dtb.read_misses 0 # DTB read misses
308system.cpu.dtb.write_hits 0 # DTB write hits
309system.cpu.dtb.write_misses 0 # DTB write misses
310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dtb.read_accesses 0 # DTB read accesses
320system.cpu.dtb.write_accesses 0 # DTB write accesses
321system.cpu.dtb.inst_accesses 0 # ITB inst accesses
322system.cpu.dtb.hits 0 # DTB hits
323system.cpu.dtb.misses 0 # DTB misses
324system.cpu.dtb.accesses 0 # DTB accesses
325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
354system.cpu.itb.walker.walks 0 # Table walker walks requested
355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.inst_hits 0 # ITB inst hits
363system.cpu.itb.inst_misses 0 # ITB inst misses
364system.cpu.itb.read_hits 0 # DTB read hits
365system.cpu.itb.read_misses 0 # DTB read misses
366system.cpu.itb.write_hits 0 # DTB write hits
367system.cpu.itb.write_misses 0 # DTB write misses
368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
370system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
371system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
372system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
373system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
374system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
375system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.itb.read_accesses 0 # DTB read accesses
378system.cpu.itb.write_accesses 0 # DTB write accesses
379system.cpu.itb.inst_accesses 0 # ITB inst accesses
380system.cpu.itb.hits 0 # DTB hits
381system.cpu.itb.misses 0 # DTB misses
382system.cpu.itb.accesses 0 # DTB accesses
383system.cpu.workload.num_syscalls 400 # Number of system calls
384system.cpu.numCycles 170980863 # number of cpu cycles simulated
385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
387system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss
388system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed
389system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered
390system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken
391system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked
392system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing
393system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
394system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions
395system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR
396system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched
397system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed
398system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle
411system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle
412system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle
413system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked
414system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running
415system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking
416system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing
417system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch
418system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction
419system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode
420system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode
421system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing
422system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle
423system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking
424system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst
425system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running
426system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking
427system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename
428system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename
429system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full
430system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full
431system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full
432system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full
433system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers
434system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed
435system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made
436system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups
437system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups
438system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
439system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing
440system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed
441system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed
442system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer
443system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit.
444system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit.
445system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads.
446system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores.
447system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec)
448system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ
449system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued
450system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued
451system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling
452system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph
453system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed
454system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
470system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle
471system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
472system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available
473system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available
474system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available
475system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available
476system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available
477system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available
478system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available
479system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available
480system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available
500system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available
501system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available
502system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available
503system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
504system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
505system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
506system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued
507system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued
508system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
509system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
510system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
511system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
512system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
513system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
514system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued
535system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued
536system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued
537system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
538system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
539system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued
540system.cpu.iq.rate 1.256951 # Inst issue rate
541system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested
542system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst)
543system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads
544system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes
545system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses
546system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads
547system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes
548system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses
549system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses
550system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses
551system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores
552system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
553system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed
554system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed
555system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations
556system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed
557system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
558system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
559system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled
560system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked
561system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
562system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing
563system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking
564system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking
565system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ
566system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
567system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions
568system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions
569system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions
570system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall
571system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall
572system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations
573system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly
574system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly
575system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute
576system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions
577system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed
578system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute
579system.cpu.iew.exec_swp 0 # number of swp insts executed
580system.cpu.iew.exec_nop 15961 # number of nop insts executed
581system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed
582system.cpu.iew.exec_branches 44936158 # Number of branches executed
583system.cpu.iew.exec_stores 13139841 # Number of stores executed
584system.cpu.iew.exec_rate 1.213760 # Inst execution rate
585system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit
586system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back
587system.cpu.iew.wb_producers 129474820 # num instructions producing a value
588system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value
589system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle
590system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back
591system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit
592system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
593system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted
594system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle
595system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle
611system.cpu.commit.committedInsts 172317410 # Number of instructions committed
612system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
613system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
614system.cpu.commit.refs 40540778 # Number of memory references committed
615system.cpu.commit.loads 27896144 # Number of loads committed
616system.cpu.commit.membars 22408 # Number of memory barriers committed
617system.cpu.commit.branches 40300312 # Number of branches committed
618system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
619system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
620system.cpu.commit.function_calls 1848934 # Number of function calls committed.
621system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
622system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction
623system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
624system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
625system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
626system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
627system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
628system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
629system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
630system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
631system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
632system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
633system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
634system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
635system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
636system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
637system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
638system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
639system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
640system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
641system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
642system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
643system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
644system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
645system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
646system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
647system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
648system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
649system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
650system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
651system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
652system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
653system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
654system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
655system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction
656system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached
657system.cpu.rob.rob_reads 406631126 # The number of ROB reads
658system.cpu.rob.rob_writes 513844376 # The number of ROB writes
659system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself
660system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling
661system.cpu.committedInsts 172303022 # Number of Instructions Simulated
662system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated
663system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction
664system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads
665system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle
666system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads
667system.cpu.int_regfile_reads 218966975 # number of integer regfile reads
668system.cpu.int_regfile_writes 114516229 # number of integer regfile writes
669system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads
670system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes
671system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads
672system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes
673system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads
674system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
675system.cpu.dcache.tags.replacements 72854 # number of replacements
676system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use
677system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks.
678system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks.
679system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks.
680system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit.
681system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor
682system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy
683system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy
684system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
685system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
686system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
687system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id
688system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
689system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
690system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
691system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses
692system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses
693system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits
694system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits
695system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits
696system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits
697system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits
698system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits
699system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits
700system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits
701system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
702system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
703system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits
704system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits
705system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits
706system.cpu.dcache.overall_hits::total 41069884 # number of overall hits
707system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses
708system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses
709system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses
710system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses
711system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses
712system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses
713system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses
714system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses
715system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses
716system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses
717system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses
718system.cpu.dcache.overall_misses::total 112572 # number of overall misses
719system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles
720system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles
721system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles
722system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles
723system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles
724system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles
725system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles
726system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles
727system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles
728system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles
729system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses)
730system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses)
731system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
732system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
733system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses)
734system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses)
735system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
736system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
737system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
738system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
739system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses
740system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses
741system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses
742system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses
743system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses
744system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses
745system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses
746system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses
747system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses
748system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses
749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses
750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses
751system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses
752system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses
753system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses
754system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses
755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency
756system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency
757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency
758system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency
759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency
760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency
761system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency
762system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency
763system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency
764system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency
765system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked
766system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked
767system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
768system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked
769system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked
770system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked
771system.cpu.dcache.fast_writes 0 # number of fast writes performed
772system.cpu.dcache.cache_copies 0 # number of cache copies performed
773system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks
774system.cpu.dcache.writebacks::total 72854 # number of writebacks
775system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits
776system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits
777system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits
778system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits
779system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits
780system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits
781system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits
782system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits
783system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits
784system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits
785system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses
786system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses
787system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses
788system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses
789system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses
790system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses
791system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses
792system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses
793system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses
794system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses
795system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles
796system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles
797system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles
798system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles
799system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles
800system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles
801system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles
802system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles
803system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles
804system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles
805system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses
806system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses
807system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses
808system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses
809system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses
810system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses
811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses
812system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses
813system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses
814system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency
816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency
817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency
818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency
819system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency
820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency
821system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency
822system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency
823system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency
824system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency
825system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
826system.cpu.icache.tags.replacements 54401 # number of replacements
827system.cpu.icache.tags.tagsinuse 510.602972 # Cycle average of tags in use
828system.cpu.icache.tags.total_refs 78901806 # Total number of references to valid blocks.
829system.cpu.icache.tags.sampled_refs 54913 # Sample count of references to valid blocks.
830system.cpu.icache.tags.avg_refs 1436.851128 # Average number of references to valid blocks.
831system.cpu.icache.tags.warmup_cycle 84733597500 # Cycle when the warmup percentage was hit.
832system.cpu.icache.tags.occ_blocks::cpu.inst 510.602972 # Average occupied blocks per requestor
833system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy
834system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy
835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
836system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
837system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
838system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
839system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
840system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
842system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses
843system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses
844system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits
845system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits
846system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits
847system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits
848system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits
849system.cpu.icache.overall_hits::total 78901806 # number of overall hits
850system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses
851system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses
852system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses
853system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses
854system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses
855system.cpu.icache.overall_misses::total 58402 # number of overall misses
856system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles
857system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles
858system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles
859system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles
860system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles
861system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles
862system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses)
863system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses)
864system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses
865system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses
866system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses
867system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses
868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses
869system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses
870system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses
871system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses
872system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # miss rate for overall accesses
873system.cpu.icache.overall_miss_rate::total 0.000740 # miss rate for overall accesses
874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772 # average ReadReq miss latency
875system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772 # average ReadReq miss latency
876system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency
877system.cpu.icache.demand_avg_miss_latency::total 19811.965772 # average overall miss latency
878system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency
879system.cpu.icache.overall_avg_miss_latency::total 19811.965772 # average overall miss latency
880system.cpu.icache.blocked_cycles::no_mshrs 72401 # number of cycles access was blocked
881system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked
882system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked
883system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
884system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked
885system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked
886system.cpu.icache.fast_writes 0 # number of fast writes performed
887system.cpu.icache.cache_copies 0 # number of cache copies performed
888system.cpu.icache.writebacks::writebacks 54401 # number of writebacks
889system.cpu.icache.writebacks::total 54401 # number of writebacks
890system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits
891system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits
892system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # number of demand (read+write) MSHR hits
893system.cpu.icache.demand_mshr_hits::total 3488 # number of demand (read+write) MSHR hits
894system.cpu.icache.overall_mshr_hits::cpu.inst 3488 # number of overall MSHR hits
895system.cpu.icache.overall_mshr_hits::total 3488 # number of overall MSHR hits
896system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54914 # number of ReadReq MSHR misses
897system.cpu.icache.ReadReq_mshr_misses::total 54914 # number of ReadReq MSHR misses
898system.cpu.icache.demand_mshr_misses::cpu.inst 54914 # number of demand (read+write) MSHR misses
899system.cpu.icache.demand_mshr_misses::total 54914 # number of demand (read+write) MSHR misses
900system.cpu.icache.overall_mshr_misses::cpu.inst 54914 # number of overall MSHR misses
901system.cpu.icache.overall_mshr_misses::total 54914 # number of overall MSHR misses
902system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1043630451 # number of ReadReq MSHR miss cycles
903system.cpu.icache.ReadReq_mshr_miss_latency::total 1043630451 # number of ReadReq MSHR miss cycles
904system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1043630451 # number of demand (read+write) MSHR miss cycles
905system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles
906system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles
907system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles
908system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses
909system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses
910system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses
911system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses
912system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses
913system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses
914system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # average ReadReq mshr miss latency
915system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730 # average ReadReq mshr miss latency
916system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency
917system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency
918system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency
919system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency
920system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
921system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued
922system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified
923system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
924system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
925system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
926system.cpu.l2cache.prefetcher.pfSpanPage 1359 # number of prefetches not generated due to page crossing
927system.cpu.l2cache.tags.replacements 0 # number of replacements
928system.cpu.l2cache.tags.tagsinuse 2148.551192 # Cycle average of tags in use
929system.cpu.l2cache.tags.total_refs 159756 # Total number of references to valid blocks.
930system.cpu.l2cache.tags.sampled_refs 3199 # Sample count of references to valid blocks.
931system.cpu.l2cache.tags.avg_refs 49.939356 # Average number of references to valid blocks.
932system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
933system.cpu.l2cache.tags.occ_blocks::writebacks 1987.164357 # Average occupied blocks per requestor
934system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 161.386835 # Average occupied blocks per requestor
935system.cpu.l2cache.tags.occ_percent::writebacks 0.121287 # Average percentage of cache occupancy
936system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009850 # Average percentage of cache occupancy
937system.cpu.l2cache.tags.occ_percent::total 0.131137 # Average percentage of cache occupancy
938system.cpu.l2cache.tags.occ_task_id_blocks::1022 254 # Occupied blocks per task id
939system.cpu.l2cache.tags.occ_task_id_blocks::1024 2945 # Occupied blocks per task id
940system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
941system.cpu.l2cache.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id
942system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id
943system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
944system.cpu.l2cache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id
945system.cpu.l2cache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id
946system.cpu.l2cache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
947system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1654 # Occupied blocks per task id
948system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id
949system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179749 # Percentage of cache occupancy per task id
950system.cpu.l2cache.tags.tag_accesses 3989175 # Number of tag accesses
951system.cpu.l2cache.tags.data_accesses 3989175 # Number of data accesses
952system.cpu.l2cache.WritebackDirty_hits::writebacks 64840 # number of WritebackDirty hits
953system.cpu.l2cache.WritebackDirty_hits::total 64840 # number of WritebackDirty hits
954system.cpu.l2cache.WritebackClean_hits::writebacks 51941 # number of WritebackClean hits
955system.cpu.l2cache.WritebackClean_hits::total 51941 # number of WritebackClean hits
956system.cpu.l2cache.ReadExReq_hits::cpu.data 8403 # number of ReadExReq hits
957system.cpu.l2cache.ReadExReq_hits::total 8403 # number of ReadExReq hits
958system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 45734 # number of ReadCleanReq hits
959system.cpu.l2cache.ReadCleanReq_hits::total 45734 # number of ReadCleanReq hits
960system.cpu.l2cache.ReadSharedReq_hits::cpu.data 62891 # number of ReadSharedReq hits
961system.cpu.l2cache.ReadSharedReq_hits::total 62891 # number of ReadSharedReq hits
962system.cpu.l2cache.demand_hits::cpu.inst 45734 # number of demand (read+write) hits
963system.cpu.l2cache.demand_hits::cpu.data 71294 # number of demand (read+write) hits
964system.cpu.l2cache.demand_hits::total 117028 # number of demand (read+write) hits
965system.cpu.l2cache.overall_hits::cpu.inst 45734 # number of overall hits
966system.cpu.l2cache.overall_hits::cpu.data 71294 # number of overall hits
967system.cpu.l2cache.overall_hits::total 117028 # number of overall hits
968system.cpu.l2cache.ReadExReq_misses::cpu.data 237 # number of ReadExReq misses
969system.cpu.l2cache.ReadExReq_misses::total 237 # number of ReadExReq misses
970system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9180 # number of ReadCleanReq misses
971system.cpu.l2cache.ReadCleanReq_misses::total 9180 # number of ReadCleanReq misses
972system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1835 # number of ReadSharedReq misses
973system.cpu.l2cache.ReadSharedReq_misses::total 1835 # number of ReadSharedReq misses
974system.cpu.l2cache.demand_misses::cpu.inst 9180 # number of demand (read+write) misses
975system.cpu.l2cache.demand_misses::cpu.data 2072 # number of demand (read+write) misses
976system.cpu.l2cache.demand_misses::total 11252 # number of demand (read+write) misses
977system.cpu.l2cache.overall_misses::cpu.inst 9180 # number of overall misses
978system.cpu.l2cache.overall_misses::cpu.data 2072 # number of overall misses
979system.cpu.l2cache.overall_misses::total 11252 # number of overall misses
980system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19043000 # number of ReadExReq miss cycles
981system.cpu.l2cache.ReadExReq_miss_latency::total 19043000 # number of ReadExReq miss cycles
982system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 687767000 # number of ReadCleanReq miss cycles
983system.cpu.l2cache.ReadCleanReq_miss_latency::total 687767000 # number of ReadCleanReq miss cycles
984system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 141031000 # number of ReadSharedReq miss cycles
985system.cpu.l2cache.ReadSharedReq_miss_latency::total 141031000 # number of ReadSharedReq miss cycles
986system.cpu.l2cache.demand_miss_latency::cpu.inst 687767000 # number of demand (read+write) miss cycles
987system.cpu.l2cache.demand_miss_latency::cpu.data 160074000 # number of demand (read+write) miss cycles
988system.cpu.l2cache.demand_miss_latency::total 847841000 # number of demand (read+write) miss cycles
989system.cpu.l2cache.overall_miss_latency::cpu.inst 687767000 # number of overall miss cycles
990system.cpu.l2cache.overall_miss_latency::cpu.data 160074000 # number of overall miss cycles
991system.cpu.l2cache.overall_miss_latency::total 847841000 # number of overall miss cycles
992system.cpu.l2cache.WritebackDirty_accesses::writebacks 64840 # number of WritebackDirty accesses(hits+misses)
993system.cpu.l2cache.WritebackDirty_accesses::total 64840 # number of WritebackDirty accesses(hits+misses)
994system.cpu.l2cache.WritebackClean_accesses::writebacks 51941 # number of WritebackClean accesses(hits+misses)
995system.cpu.l2cache.WritebackClean_accesses::total 51941 # number of WritebackClean accesses(hits+misses)
996system.cpu.l2cache.ReadExReq_accesses::cpu.data 8640 # number of ReadExReq accesses(hits+misses)
997system.cpu.l2cache.ReadExReq_accesses::total 8640 # number of ReadExReq accesses(hits+misses)
998system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54914 # number of ReadCleanReq accesses(hits+misses)
999system.cpu.l2cache.ReadCleanReq_accesses::total 54914 # number of ReadCleanReq accesses(hits+misses)
1000system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64726 # number of ReadSharedReq accesses(hits+misses)
1001system.cpu.l2cache.ReadSharedReq_accesses::total 64726 # number of ReadSharedReq accesses(hits+misses)
1002system.cpu.l2cache.demand_accesses::cpu.inst 54914 # number of demand (read+write) accesses
1003system.cpu.l2cache.demand_accesses::cpu.data 73366 # number of demand (read+write) accesses
1004system.cpu.l2cache.demand_accesses::total 128280 # number of demand (read+write) accesses
1005system.cpu.l2cache.overall_accesses::cpu.inst 54914 # number of overall (read+write) accesses
1006system.cpu.l2cache.overall_accesses::cpu.data 73366 # number of overall (read+write) accesses
1007system.cpu.l2cache.overall_accesses::total 128280 # number of overall (read+write) accesses
1008system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027431 # miss rate for ReadExReq accesses
1009system.cpu.l2cache.ReadExReq_miss_rate::total 0.027431 # miss rate for ReadExReq accesses
1010system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167170 # miss rate for ReadCleanReq accesses
1011system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167170 # miss rate for ReadCleanReq accesses
1012system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.028350 # miss rate for ReadSharedReq accesses
1013system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.028350 # miss rate for ReadSharedReq accesses
1014system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167170 # miss rate for demand accesses
1015system.cpu.l2cache.demand_miss_rate::cpu.data 0.028242 # miss rate for demand accesses
1016system.cpu.l2cache.demand_miss_rate::total 0.087714 # miss rate for demand accesses
1017system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167170 # miss rate for overall accesses
1018system.cpu.l2cache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses
1019system.cpu.l2cache.overall_miss_rate::total 0.087714 # miss rate for overall accesses
1020system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80350.210970 # average ReadExReq miss latency
1021system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80350.210970 # average ReadExReq miss latency
1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74920.152505 # average ReadCleanReq miss latency
1023system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74920.152505 # average ReadCleanReq miss latency
1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76856.130790 # average ReadSharedReq miss latency
1025system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76856.130790 # average ReadSharedReq miss latency
1026system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74920.152505 # average overall miss latency
1027system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77255.791506 # average overall miss latency
1028system.cpu.l2cache.demand_avg_miss_latency::total 75350.248845 # average overall miss latency
1029system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74920.152505 # average overall miss latency
1030system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77255.791506 # average overall miss latency
1031system.cpu.l2cache.overall_avg_miss_latency::total 75350.248845 # average overall miss latency
1032system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1033system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1034system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1035system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1036system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1037system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1038system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1039system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1040system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
1041system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
1042system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
1043system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
1044system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
1045system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
1046system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
1047system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
1048system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
1049system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
1050system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
1051system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
1052system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2046 # number of HardPFReq MSHR misses
1053system.cpu.l2cache.HardPFReq_mshr_misses::total 2046 # number of HardPFReq MSHR misses
1054system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses
1055system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses
1056system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9175 # number of ReadCleanReq MSHR misses
1057system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9175 # number of ReadCleanReq MSHR misses
1058system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1827 # number of ReadSharedReq MSHR misses
1059system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1827 # number of ReadSharedReq MSHR misses
1060system.cpu.l2cache.demand_mshr_misses::cpu.inst 9175 # number of demand (read+write) MSHR misses
1061system.cpu.l2cache.demand_mshr_misses::cpu.data 2063 # number of demand (read+write) MSHR misses
1062system.cpu.l2cache.demand_mshr_misses::total 11238 # number of demand (read+write) MSHR misses
1063system.cpu.l2cache.overall_mshr_misses::cpu.inst 9175 # number of overall MSHR misses
1064system.cpu.l2cache.overall_mshr_misses::cpu.data 2063 # number of overall MSHR misses
1065system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2046 # number of overall MSHR misses
1066system.cpu.l2cache.overall_mshr_misses::total 13284 # number of overall MSHR misses
1067system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of HardPFReq MSHR miss cycles
1068system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66908651 # number of HardPFReq MSHR miss cycles
1069system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17421000 # number of ReadExReq MSHR miss cycles
1070system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17421000 # number of ReadExReq MSHR miss cycles
1071system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 632417000 # number of ReadCleanReq MSHR miss cycles
1072system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 632417000 # number of ReadCleanReq MSHR miss cycles
1073system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 129587000 # number of ReadSharedReq MSHR miss cycles
1074system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 129587000 # number of ReadSharedReq MSHR miss cycles
1075system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 632417000 # number of demand (read+write) MSHR miss cycles
1076system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147008000 # number of demand (read+write) MSHR miss cycles
1077system.cpu.l2cache.demand_mshr_miss_latency::total 779425000 # number of demand (read+write) MSHR miss cycles
1078system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 632417000 # number of overall MSHR miss cycles
1079system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147008000 # number of overall MSHR miss cycles
1080system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of overall MSHR miss cycles
1081system.cpu.l2cache.overall_mshr_miss_latency::total 846333651 # number of overall MSHR miss cycles
1082system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1083system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1084system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses
1085system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses
1086system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses
1087system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses
1088system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses
1089system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses
1090system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses
1091system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses
1092system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses
1093system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses
1094system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses
1095system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1096system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses
1097system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency
1098system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency
1099system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency
1100system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency
1101system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency
1102system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency
1103system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency
1104system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency
1105system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency
1106system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency
1107system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency
1108system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency
1109system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency
1110system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency
1111system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency
1112system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1113system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter.
1114system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1115system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1116system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter.
1117system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1118system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1119system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution
1120system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution
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