1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.071387 # Number of seconds simulated
4sim_ticks 71387376000 # Number of ticks simulated
5final_tick 71387376000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 91858 # Simulator instruction rate (inst/s)
8host_op_rate 96834 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38058123 # Simulator tick rate (ticks/s)
10host_mem_usage 257304 # Number of bytes of host memory used
11host_seconds 1875.75 # Real time elapsed on the host
12sim_insts 172303021 # Number of instructions simulated
13sim_ops 181635953 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 130496 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 111040 # Number of bytes read from this memory
18system.physmem.bytes_read::total 241536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 130496 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 130496 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2039 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1735 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 3774 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 1827998 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 1555457 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 3383455 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 1827998 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 1827998 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 1827998 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 1555457 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 3383455 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 3774 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 3774 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 241536 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 241536 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 60 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 313 # Per bank write bursts
45system.physmem.perBankRdBursts::1 214 # Per bank write bursts
46system.physmem.perBankRdBursts::2 128 # Per bank write bursts
47system.physmem.perBankRdBursts::3 306 # Per bank write bursts
48system.physmem.perBankRdBursts::4 297 # Per bank write bursts
49system.physmem.perBankRdBursts::5 299 # Per bank write bursts
50system.physmem.perBankRdBursts::6 265 # Per bank write bursts
51system.physmem.perBankRdBursts::7 217 # Per bank write bursts
52system.physmem.perBankRdBursts::8 243 # Per bank write bursts
53system.physmem.perBankRdBursts::9 220 # Per bank write bursts
54system.physmem.perBankRdBursts::10 282 # Per bank write bursts
55system.physmem.perBankRdBursts::11 189 # Per bank write bursts
56system.physmem.perBankRdBursts::12 184 # Per bank write bursts
57system.physmem.perBankRdBursts::13 208 # Per bank write bursts
58system.physmem.perBankRdBursts::14 212 # Per bank write bursts
59system.physmem.perBankRdBursts::15 197 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 71387262500 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 3774 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 2817 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 790 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 125 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

--- 64 unchanged lines hidden (view full) ---

181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 730 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 328.591781 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 199.502533 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 324.063907 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 243 33.29% 33.29% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 162 22.19% 55.48% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 95 13.01% 68.49% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 41 5.62% 74.11% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 34 4.66% 78.77% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 29 3.97% 82.74% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 36 4.93% 87.67% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 21 2.88% 90.55% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 69 9.45% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 730 # Bytes accessed per row activation
203system.physmem.totQLat 27328250 # Total ticks spent queuing
204system.physmem.totMemAccLat 98090750 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 18870000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 7241.19 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 25991.19 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 3.38 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 3.38 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 0.03 # Data bus utilization in percentage
215system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 3037 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 18915543.85 # Average gap between requests
224system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined
225system.physmem.memoryStateTime::IDLE 68189011250 # Time in different power states
226system.physmem.memoryStateTime::REF 2383680000 # Time in different power states
227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
228system.physmem.memoryStateTime::ACT 812104750 # Time in different power states
229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
230system.membus.throughput 3383455 # Throughput (bytes/s)
231system.membus.trans_dist::ReadReq 2699 # Transaction distribution
232system.membus.trans_dist::ReadResp 2699 # Transaction distribution
233system.membus.trans_dist::UpgradeReq 60 # Transaction distribution
234system.membus.trans_dist::UpgradeResp 60 # Transaction distribution
235system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
236system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7668 # Packet count per connected master and slave (bytes)
238system.membus.pkt_count::total 7668 # Packet count per connected master and slave (bytes)
239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 241536 # Cumulative packet size per connected master and slave (bytes)
240system.membus.tot_pkt_size::total 241536 # Cumulative packet size per connected master and slave (bytes)
241system.membus.data_through_bus 241536 # Total data (bytes)
242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
243system.membus.reqLayer0.occupancy 4574500 # Layer occupancy (ticks)
244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
245system.membus.respLayer1.occupancy 35380947 # Layer occupancy (ticks)
246system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
247system.cpu_clk_domain.clock 500 # Clock period in ticks
248system.cpu.branchPred.lookups 106458293 # Number of BP lookups
249system.cpu.branchPred.condPredicted 82706448 # Number of conditional branches predicted
250system.cpu.branchPred.condIncorrect 6339444 # Number of conditional branches incorrect
251system.cpu.branchPred.BTBLookups 50217715 # Number of BTB lookups
252system.cpu.branchPred.BTBHits 48291708 # Number of BTB hits
253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
254system.cpu.branchPred.BTBHitPct 96.164686 # BTB Hit Percentage
255system.cpu.branchPred.usedRAS 5164625 # Number of times the RAS was used to get a target.
256system.cpu.branchPred.RASInCorrect 84625 # Number of incorrect RAS predictions.
257system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
258system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
259system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
260system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
261system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
262system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
263system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 69 unchanged lines hidden (view full) ---

334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
335system.cpu.itb.read_accesses 0 # DTB read accesses
336system.cpu.itb.write_accesses 0 # DTB write accesses
337system.cpu.itb.inst_accesses 0 # ITB inst accesses
338system.cpu.itb.hits 0 # DTB hits
339system.cpu.itb.misses 0 # DTB misses
340system.cpu.itb.accesses 0 # DTB accesses
341system.cpu.workload.num_syscalls 400 # Number of system calls
342system.cpu.numCycles 142774753 # number of cpu cycles simulated
343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
345system.cpu.fetch.icacheStallCycles 44808389 # Number of cycles fetch is stalled on an Icache miss
346system.cpu.fetch.Insts 429802861 # Number of instructions fetch has processed
347system.cpu.fetch.Branches 106458293 # Number of branches that fetch encountered
348system.cpu.fetch.predictedBranches 53456333 # Number of branches that fetch has predicted taken
349system.cpu.fetch.Cycles 91468493 # Number of cycles fetch has run and was not squashing or blocked
350system.cpu.fetch.SquashCycles 12731388 # Number of cycles fetch has spent squashing
351system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
352system.cpu.fetch.PendingTrapStallCycles 5563 # Number of stall cycles due to pending traps
353system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
354system.cpu.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR
355system.cpu.fetch.CacheLines 41753796 # Number of cache lines fetched
356system.cpu.fetch.IcacheSquashes 1912042 # Number of outstanding Icache misses that were squashed
357system.cpu.fetch.rateDist::samples 142648266 # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::mean 3.160575 # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::stdev 3.133574 # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::0 53718645 37.66% 37.66% # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.rateDist::1 6357410 4.46% 42.11% # Number of instructions fetched each cycle (Total)
363system.cpu.fetch.rateDist::2 10351894 7.26% 49.37% # Number of instructions fetched each cycle (Total)
364system.cpu.fetch.rateDist::3 14920250 10.46% 59.83% # Number of instructions fetched each cycle (Total)
365system.cpu.fetch.rateDist::4 10655390 7.47% 67.30% # Number of instructions fetched each cycle (Total)
366system.cpu.fetch.rateDist::5 3891108 2.73% 70.03% # Number of instructions fetched each cycle (Total)
367system.cpu.fetch.rateDist::6 7883355 5.53% 75.56% # Number of instructions fetched each cycle (Total)
368system.cpu.fetch.rateDist::7 9310317 6.53% 82.08% # Number of instructions fetched each cycle (Total)
369system.cpu.fetch.rateDist::8 25559897 17.92% 100.00% # Number of instructions fetched each cycle (Total)
370system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
371system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
372system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
373system.cpu.fetch.rateDist::total 142648266 # Number of instructions fetched each cycle (Total)
374system.cpu.fetch.branchRate 0.745638 # Number of branch fetches per cycle
375system.cpu.fetch.rate 3.010356 # Number of inst fetches per cycle
376system.cpu.decode.IdleCycles 37233141 # Number of cycles decode is idle
377system.cpu.decode.BlockedCycles 23853545 # Number of cycles decode is blocked
378system.cpu.decode.RunCycles 68602562 # Number of cycles decode is running
379system.cpu.decode.UnblockCycles 6747325 # Number of cycles decode is unblocking
380system.cpu.decode.SquashCycles 6211693 # Number of cycles decode is squashing
381system.cpu.decode.BranchResolved 15955000 # Number of times decode resolved a branch
382system.cpu.decode.BranchMispred 160395 # Number of times decode detected a branch misprediction
383system.cpu.decode.DecodedInsts 420485829 # Number of instructions handled by decode
384system.cpu.decode.SquashedInsts 828178 # Number of squashed instructions handled by decode
385system.cpu.rename.SquashCycles 6211693 # Number of cycles rename is squashing
386system.cpu.rename.IdleCycles 42171212 # Number of cycles rename is idle
387system.cpu.rename.BlockCycles 18551410 # Number of cycles rename is blocking
388system.cpu.rename.serializeStallCycles 713419 # count of cycles rename stalled for serializing inst
389system.cpu.rename.RunCycles 69222818 # Number of cycles rename is running
390system.cpu.rename.UnblockCycles 5777714 # Number of cycles rename is unblocking
391system.cpu.rename.RenamedInsts 398176302 # Number of instructions processed by rename
392system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full
393system.cpu.rename.IQFullEvents 1614739 # Number of times rename has blocked due to IQ full
394system.cpu.rename.LQFullEvents 2816561 # Number of times rename has blocked due to LQ full
395system.cpu.rename.SQFullEvents 62575 # Number of times rename has blocked due to SQ full
396system.cpu.rename.FullRegisterEvents 202 # Number of times there has been no free registers
397system.cpu.rename.RenamedOperands 691997012 # Number of destination operands rename has renamed
398system.cpu.rename.RenameLookups 1704697725 # Number of register rename lookups that rename has made
399system.cpu.rename.int_rename_lookups 425662370 # Number of integer rename lookups
400system.cpu.rename.fp_rename_lookups 3491733 # Number of floating rename lookups
401system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
402system.cpu.rename.UndoneMaps 399020083 # Number of HB maps that are undone due to squashing
403system.cpu.rename.serializingInsts 28576 # count of serializing insts renamed
404system.cpu.rename.tempSerializingInsts 28600 # count of temporary serializing insts renamed
405system.cpu.rename.skidInsts 15636023 # count of insts added to the skid buffer
406system.cpu.memDep0.insertedLoads 44518617 # Number of loads inserted to the mem dependence unit.
407system.cpu.memDep0.insertedStores 18120521 # Number of stores inserted to the mem dependence unit.
408system.cpu.memDep0.conflictingLoads 7204434 # Number of conflicting loads.
409system.cpu.memDep0.conflictingStores 5193927 # Number of conflicting stores.
410system.cpu.iq.iqInstsAdded 353303303 # Number of instructions added to the IQ (excludes non-spec)
411system.cpu.iq.iqNonSpecInstsAdded 50659 # Number of non-speculative instructions added to the IQ
412system.cpu.iq.iqInstsIssued 249217571 # Number of instructions issued
413system.cpu.iq.iqSquashedInstsIssued 532732 # Number of squashed instructions issued
414system.cpu.iq.iqSquashedInstsExamined 170449002 # Number of squashed instructions iterated over during squash; mainly for profiling
415system.cpu.iq.iqSquashedOperandsExamined 473050896 # Number of squashed operands that are examined and possibly removed from graph
416system.cpu.iq.iqSquashedNonSpecRemoved 5443 # Number of squashed non-spec instructions that were removed
417system.cpu.iq.issued_per_cycle::samples 142648266 # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::mean 1.747077 # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::stdev 1.881809 # Number of insts issued each cycle
420system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
421system.cpu.iq.issued_per_cycle::0 54008982 37.86% 37.86% # Number of insts issued each cycle
422system.cpu.iq.issued_per_cycle::1 21782256 15.27% 53.13% # Number of insts issued each cycle
423system.cpu.iq.issued_per_cycle::2 24530872 17.20% 70.33% # Number of insts issued each cycle
424system.cpu.iq.issued_per_cycle::3 16106640 11.29% 81.62% # Number of insts issued each cycle
425system.cpu.iq.issued_per_cycle::4 11858342 8.31% 89.93% # Number of insts issued each cycle
426system.cpu.iq.issued_per_cycle::5 6781839 4.75% 94.69% # Number of insts issued each cycle
427system.cpu.iq.issued_per_cycle::6 5090438 3.57% 98.26% # Number of insts issued each cycle
428system.cpu.iq.issued_per_cycle::7 1742716 1.22% 99.48% # Number of insts issued each cycle
429system.cpu.iq.issued_per_cycle::8 746181 0.52% 100.00% # Number of insts issued each cycle
430system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
431system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
432system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
433system.cpu.iq.issued_per_cycle::total 142648266 # Number of insts issued each cycle
434system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
435system.cpu.iq.fu_full::IntAlu 1599616 44.61% 44.61% # attempts to use FU when none available
436system.cpu.iq.fu_full::IntMult 5629 0.16% 44.77% # attempts to use FU when none available
437system.cpu.iq.fu_full::IntDiv 0 0.00% 44.77% # attempts to use FU when none available
438system.cpu.iq.fu_full::FloatAdd 0 0.00% 44.77% # attempts to use FU when none available
439system.cpu.iq.fu_full::FloatCmp 0 0.00% 44.77% # attempts to use FU when none available
440system.cpu.iq.fu_full::FloatCvt 0 0.00% 44.77% # attempts to use FU when none available
441system.cpu.iq.fu_full::FloatMult 0 0.00% 44.77% # attempts to use FU when none available
442system.cpu.iq.fu_full::FloatDiv 0 0.00% 44.77% # attempts to use FU when none available
443system.cpu.iq.fu_full::FloatSqrt 0 0.00% 44.77% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdAdd 0 0.00% 44.77% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 44.77% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdAlu 0 0.00% 44.77% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdCmp 0 0.00% 44.77% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdCvt 0 0.00% 44.77% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdMisc 0 0.00% 44.77% # attempts to use FU when none available
450system.cpu.iq.fu_full::SimdMult 0 0.00% 44.77% # attempts to use FU when none available
451system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 44.77% # attempts to use FU when none available
452system.cpu.iq.fu_full::SimdShift 0 0.00% 44.77% # attempts to use FU when none available
453system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 44.77% # attempts to use FU when none available
454system.cpu.iq.fu_full::SimdSqrt 0 0.00% 44.77% # attempts to use FU when none available
455system.cpu.iq.fu_full::SimdFloatAdd 43 0.00% 44.77% # attempts to use FU when none available
456system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 44.77% # attempts to use FU when none available
457system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 44.77% # attempts to use FU when none available
458system.cpu.iq.fu_full::SimdFloatCvt 26 0.00% 44.77% # attempts to use FU when none available
459system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 44.77% # attempts to use FU when none available
460system.cpu.iq.fu_full::SimdFloatMisc 2425 0.07% 44.84% # attempts to use FU when none available
461system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 44.84% # attempts to use FU when none available
462system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.84% # attempts to use FU when none available
463system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 44.84% # attempts to use FU when none available
464system.cpu.iq.fu_full::MemRead 1462989 40.80% 85.64% # attempts to use FU when none available
465system.cpu.iq.fu_full::MemWrite 515010 14.36% 100.00% # attempts to use FU when none available
466system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
467system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
468system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
469system.cpu.iq.FU_type_0::IntAlu 192832828 77.38% 77.38% # Type of FU issued
470system.cpu.iq.FU_type_0::IntMult 1041370 0.42% 77.79% # Type of FU issued
471system.cpu.iq.FU_type_0::IntDiv 0 0.00% 77.79% # Type of FU issued
472system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 77.79% # Type of FU issued
473system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 77.79% # Type of FU issued
474system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 77.79% # Type of FU issued
475system.cpu.iq.FU_type_0::FloatMult 0 0.00% 77.79% # Type of FU issued
476system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 77.79% # Type of FU issued
477system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 77.79% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 77.79% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 77.79% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 77.79% # Type of FU issued
481system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 77.79% # Type of FU issued
482system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 77.79% # Type of FU issued
483system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 77.79% # Type of FU issued
484system.cpu.iq.FU_type_0::SimdMult 0 0.00% 77.79% # Type of FU issued
485system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 77.79% # Type of FU issued
486system.cpu.iq.FU_type_0::SimdShift 0 0.00% 77.79% # Type of FU issued
487system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 77.79% # Type of FU issued
488system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 77.79% # Type of FU issued
489system.cpu.iq.FU_type_0::SimdFloatAdd 33133 0.01% 77.81% # Type of FU issued
490system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 77.81% # Type of FU issued
491system.cpu.iq.FU_type_0::SimdFloatCmp 164691 0.07% 77.87% # Type of FU issued
492system.cpu.iq.FU_type_0::SimdFloatCvt 264054 0.11% 77.98% # Type of FU issued
493system.cpu.iq.FU_type_0::SimdFloatDiv 76936 0.03% 78.01% # Type of FU issued
494system.cpu.iq.FU_type_0::SimdFloatMisc 473853 0.19% 78.20% # Type of FU issued
495system.cpu.iq.FU_type_0::SimdFloatMult 207040 0.08% 78.28% # Type of FU issued
496system.cpu.iq.FU_type_0::SimdFloatMultAcc 72084 0.03% 78.31% # Type of FU issued
497system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 78.31% # Type of FU issued
498system.cpu.iq.FU_type_0::MemRead 39374798 15.80% 94.11% # Type of FU issued
499system.cpu.iq.FU_type_0::MemWrite 14676461 5.89% 100.00% # Type of FU issued
500system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
501system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
502system.cpu.iq.FU_type_0::total 249217571 # Type of FU issued
503system.cpu.iq.rate 1.745530 # Inst issue rate
504system.cpu.iq.fu_busy_cnt 3585738 # FU busy when requested
505system.cpu.iq.fu_busy_rate 0.014388 # FU busy rate (busy events/executed inst)
506system.cpu.iq.int_inst_queue_reads 641399049 # Number of integer instruction queue reads
507system.cpu.iq.int_inst_queue_writes 521384383 # Number of integer instruction queue writes
508system.cpu.iq.int_inst_queue_wakeup_accesses 237201307 # Number of integer instruction queue wakeup accesses
509system.cpu.iq.fp_inst_queue_reads 3802829 # Number of floating instruction queue reads
510system.cpu.iq.fp_inst_queue_writes 2450137 # Number of floating instruction queue writes
511system.cpu.iq.fp_inst_queue_wakeup_accesses 1875104 # Number of floating instruction queue wakeup accesses
512system.cpu.iq.int_alu_accesses 250898873 # Number of integer alu accesses
513system.cpu.iq.fp_alu_accesses 1904436 # Number of floating point alu accesses
514system.cpu.iew.lsq.thread0.forwLoads 1999527 # Number of loads that had data forwarded from stores
515system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
516system.cpu.iew.lsq.thread0.squashedLoads 16622473 # Number of loads squashed
517system.cpu.iew.lsq.thread0.ignoredResponses 18079 # Number of memory responses ignored because the instruction is squashed
518system.cpu.iew.lsq.thread0.memOrderViolation 32569 # Number of memory ordering violations
519system.cpu.iew.lsq.thread0.squashedStores 5475887 # Number of stores squashed
520system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
521system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
522system.cpu.iew.lsq.thread0.rescheduledLoads 334532 # Number of loads that were rescheduled
523system.cpu.iew.lsq.thread0.cacheBlocked 126 # Number of times an access to memory failed due to the cache being blocked
524system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
525system.cpu.iew.iewSquashCycles 6211693 # Number of cycles IEW is squashing
526system.cpu.iew.iewBlockCycles 18514097 # Number of cycles IEW is blocking
527system.cpu.iew.iewUnblockCycles 29892 # Number of cycles IEW is unblocking
528system.cpu.iew.iewDispatchedInsts 353371291 # Number of instructions dispatched to IQ
529system.cpu.iew.iewDispSquashedInsts 723756 # Number of squashed instructions skipped by dispatch
530system.cpu.iew.iewDispLoadInsts 44518617 # Number of dispatched load instructions
531system.cpu.iew.iewDispStoreInsts 18120521 # Number of dispatched store instructions
532system.cpu.iew.iewDispNonSpecInsts 28251 # Number of dispatched non-speculative instructions
533system.cpu.iew.iewIQFullEvents 2286 # Number of times the IQ has become full, causing a stall
534system.cpu.iew.iewLSQFullEvents 27735 # Number of times the LSQ has become full, causing a stall
535system.cpu.iew.memOrderViolationEvents 32569 # Number of memory order violations
536system.cpu.iew.predictedTakenIncorrect 3999566 # Number of branches that were predicted taken incorrectly
537system.cpu.iew.predictedNotTakenIncorrect 3827175 # Number of branches that were predicted not taken incorrectly
538system.cpu.iew.branchMispredicts 7826741 # Number of branch mispredicts detected at execute
539system.cpu.iew.iewExecutedInsts 243157329 # Number of executed instructions
540system.cpu.iew.iewExecLoadInsts 37609930 # Number of load instructions executed
541system.cpu.iew.iewExecSquashedInsts 6060242 # Number of squashed instructions skipped in execute
542system.cpu.iew.exec_swp 0 # number of swp insts executed
543system.cpu.iew.exec_nop 17329 # number of nop insts executed
544system.cpu.iew.exec_refs 51859202 # number of memory reference insts executed
545system.cpu.iew.exec_branches 55857945 # Number of branches executed
546system.cpu.iew.exec_stores 14249272 # Number of stores executed
547system.cpu.iew.exec_rate 1.703084 # Inst execution rate
548system.cpu.iew.wb_sent 240511751 # cumulative count of insts sent to commit
549system.cpu.iew.wb_count 239076411 # cumulative count of insts written-back
550system.cpu.iew.wb_producers 145760285 # num instructions producing a value
551system.cpu.iew.wb_consumers 269855272 # num instructions consuming a value
552system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
553system.cpu.iew.wb_rate 1.674501 # insts written-back per cycle
554system.cpu.iew.wb_fanout 0.540142 # average fanout of values written-back
555system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
556system.cpu.commit.commitSquashedInsts 171723245 # The number of squashed insts skipped by commit
557system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
558system.cpu.commit.branchMispredicts 6185443 # The number of times a branch was mispredicted
559system.cpu.commit.committed_per_cycle::samples 117932320 # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::mean 1.540293 # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::stdev 2.243745 # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::0 51372616 43.56% 43.56% # Number of insts commited each cycle
564system.cpu.commit.committed_per_cycle::1 31468321 26.68% 70.24% # Number of insts commited each cycle
565system.cpu.commit.committed_per_cycle::2 11935963 10.12% 80.37% # Number of insts commited each cycle
566system.cpu.commit.committed_per_cycle::3 6951478 5.89% 86.26% # Number of insts commited each cycle
567system.cpu.commit.committed_per_cycle::4 3813624 3.23% 89.49% # Number of insts commited each cycle
568system.cpu.commit.committed_per_cycle::5 1418078 1.20% 90.70% # Number of insts commited each cycle
569system.cpu.commit.committed_per_cycle::6 1525333 1.29% 91.99% # Number of insts commited each cycle
570system.cpu.commit.committed_per_cycle::7 1616480 1.37% 93.36% # Number of insts commited each cycle
571system.cpu.commit.committed_per_cycle::8 7830427 6.64% 100.00% # Number of insts commited each cycle
572system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
573system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
574system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
575system.cpu.commit.committed_per_cycle::total 117932320 # Number of insts commited each cycle
576system.cpu.commit.committedInsts 172317409 # Number of instructions committed
577system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed
578system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
579system.cpu.commit.refs 40540778 # Number of memory references committed
580system.cpu.commit.loads 27896144 # Number of loads committed
581system.cpu.commit.membars 22408 # Number of memory barriers committed
582system.cpu.commit.branches 40300311 # Number of branches committed
583system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.

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613system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
614system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
615system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
616system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
617system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
618system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
619system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
620system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction
621system.cpu.commit.bw_lim_events 7830427 # number cycles where commit BW limit reached
622system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
623system.cpu.rob.rob_reads 463470278 # The number of ROB reads
624system.cpu.rob.rob_writes 731648814 # The number of ROB writes
625system.cpu.timesIdled 1645 # Number of times that the entire CPU went into an idle state and unscheduled itself
626system.cpu.idleCycles 126487 # Total number of cycles that the CPU has spent unscheduled due to idling
627system.cpu.committedInsts 172303021 # Number of Instructions Simulated
628system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated
629system.cpu.cpi 0.828626 # CPI: Cycles Per Instruction
630system.cpu.cpi_total 0.828626 # CPI: Total CPI of All Threads
631system.cpu.ipc 1.206817 # IPC: Instructions Per Cycle
632system.cpu.ipc_total 1.206817 # IPC: Total IPC of All Threads
633system.cpu.int_regfile_reads 248213314 # number of integer regfile reads
634system.cpu.int_regfile_writes 133191535 # number of integer regfile writes
635system.cpu.fp_regfile_reads 2934311 # number of floating regfile reads
636system.cpu.fp_regfile_writes 2552498 # number of floating regfile writes
637system.cpu.cc_regfile_reads 830988511 # number of cc regfile reads
638system.cpu.cc_regfile_writes 255127381 # number of cc regfile writes
639system.cpu.misc_regfile_reads 66039150 # number of misc regfile reads
640system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
641system.cpu.toL2Bus.throughput 5345035 # Throughput (bytes/s)
642system.cpu.toL2Bus.trans_dist::ReadReq 4859 # Transaction distribution
643system.cpu.toL2Bus.trans_dist::ReadResp 4858 # Transaction distribution
644system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution
645system.cpu.toL2Bus.trans_dist::UpgradeReq 61 # Transaction distribution
646system.cpu.toL2Bus.trans_dist::UpgradeResp 61 # Transaction distribution
647system.cpu.toL2Bus.trans_dist::ReadExReq 1087 # Transaction distribution
648system.cpu.toL2Bus.trans_dist::ReadExResp 1087 # Transaction distribution
649system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8146 # Packet count per connected master and slave (bytes)
650system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3823 # Packet count per connected master and slave (bytes)
651system.cpu.toL2Bus.pkt_count::total 11969 # Packet count per connected master and slave (bytes)
652system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 258688 # Cumulative packet size per connected master and slave (bytes)
653system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 118976 # Cumulative packet size per connected master and slave (bytes)
654system.cpu.toL2Bus.tot_pkt_size::total 377664 # Cumulative packet size per connected master and slave (bytes)
655system.cpu.toL2Bus.data_through_bus 377664 # Total data (bytes)
656system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes)
657system.cpu.toL2Bus.reqLayer0.occupancy 3029000 # Layer occupancy (ticks)
658system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
659system.cpu.toL2Bus.respLayer0.occupancy 6522997 # Layer occupancy (ticks)
660system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
661system.cpu.toL2Bus.respLayer1.occupancy 3106540 # Layer occupancy (ticks)
662system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
663system.cpu.icache.tags.replacements 2317 # number of replacements
664system.cpu.icache.tags.tagsinuse 1337.456920 # Cycle average of tags in use
665system.cpu.icache.tags.total_refs 41747829 # Total number of references to valid blocks.
666system.cpu.icache.tags.sampled_refs 4039 # Sample count of references to valid blocks.
667system.cpu.icache.tags.avg_refs 10336.179500 # Average number of references to valid blocks.
668system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
669system.cpu.icache.tags.occ_blocks::cpu.inst 1337.456920 # Average occupied blocks per requestor
670system.cpu.icache.tags.occ_percent::cpu.inst 0.653055 # Average percentage of cache occupancy
671system.cpu.icache.tags.occ_percent::total 0.653055 # Average percentage of cache occupancy
672system.cpu.icache.tags.occ_task_id_blocks::1024 1722 # Occupied blocks per task id
673system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
674system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id
675system.cpu.icache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id
676system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
677system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id
678system.cpu.icache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id
679system.cpu.icache.tags.tag_accesses 83511695 # Number of tag accesses
680system.cpu.icache.tags.data_accesses 83511695 # Number of data accesses
681system.cpu.icache.ReadReq_hits::cpu.inst 41748272 # number of ReadReq hits
682system.cpu.icache.ReadReq_hits::total 41748272 # number of ReadReq hits
683system.cpu.icache.demand_hits::cpu.inst 41748272 # number of demand (read+write) hits
684system.cpu.icache.demand_hits::total 41748272 # number of demand (read+write) hits
685system.cpu.icache.overall_hits::cpu.inst 41748272 # number of overall hits
686system.cpu.icache.overall_hits::total 41748272 # number of overall hits
687system.cpu.icache.ReadReq_misses::cpu.inst 5524 # number of ReadReq misses
688system.cpu.icache.ReadReq_misses::total 5524 # number of ReadReq misses
689system.cpu.icache.demand_misses::cpu.inst 5524 # number of demand (read+write) misses
690system.cpu.icache.demand_misses::total 5524 # number of demand (read+write) misses
691system.cpu.icache.overall_misses::cpu.inst 5524 # number of overall misses
692system.cpu.icache.overall_misses::total 5524 # number of overall misses
693system.cpu.icache.ReadReq_miss_latency::cpu.inst 227823494 # number of ReadReq miss cycles
694system.cpu.icache.ReadReq_miss_latency::total 227823494 # number of ReadReq miss cycles
695system.cpu.icache.demand_miss_latency::cpu.inst 227823494 # number of demand (read+write) miss cycles
696system.cpu.icache.demand_miss_latency::total 227823494 # number of demand (read+write) miss cycles
697system.cpu.icache.overall_miss_latency::cpu.inst 227823494 # number of overall miss cycles
698system.cpu.icache.overall_miss_latency::total 227823494 # number of overall miss cycles
699system.cpu.icache.ReadReq_accesses::cpu.inst 41753796 # number of ReadReq accesses(hits+misses)
700system.cpu.icache.ReadReq_accesses::total 41753796 # number of ReadReq accesses(hits+misses)
701system.cpu.icache.demand_accesses::cpu.inst 41753796 # number of demand (read+write) accesses
702system.cpu.icache.demand_accesses::total 41753796 # number of demand (read+write) accesses
703system.cpu.icache.overall_accesses::cpu.inst 41753796 # number of overall (read+write) accesses
704system.cpu.icache.overall_accesses::total 41753796 # number of overall (read+write) accesses
705system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000132 # miss rate for ReadReq accesses
706system.cpu.icache.ReadReq_miss_rate::total 0.000132 # miss rate for ReadReq accesses
707system.cpu.icache.demand_miss_rate::cpu.inst 0.000132 # miss rate for demand accesses
708system.cpu.icache.demand_miss_rate::total 0.000132 # miss rate for demand accesses
709system.cpu.icache.overall_miss_rate::cpu.inst 0.000132 # miss rate for overall accesses
710system.cpu.icache.overall_miss_rate::total 0.000132 # miss rate for overall accesses
711system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41242.486242 # average ReadReq miss latency
712system.cpu.icache.ReadReq_avg_miss_latency::total 41242.486242 # average ReadReq miss latency
713system.cpu.icache.demand_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency
714system.cpu.icache.demand_avg_miss_latency::total 41242.486242 # average overall miss latency
715system.cpu.icache.overall_avg_miss_latency::cpu.inst 41242.486242 # average overall miss latency
716system.cpu.icache.overall_avg_miss_latency::total 41242.486242 # average overall miss latency
717system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked
718system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
719system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked
720system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
721system.cpu.icache.avg_blocked_cycles::no_mshrs 47.611111 # average number of cycles each access was blocked
722system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
723system.cpu.icache.fast_writes 0 # number of fast writes performed
724system.cpu.icache.cache_copies 0 # number of cache copies performed
725system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1420 # number of ReadReq MSHR hits
726system.cpu.icache.ReadReq_mshr_hits::total 1420 # number of ReadReq MSHR hits
727system.cpu.icache.demand_mshr_hits::cpu.inst 1420 # number of demand (read+write) MSHR hits
728system.cpu.icache.demand_mshr_hits::total 1420 # number of demand (read+write) MSHR hits
729system.cpu.icache.overall_mshr_hits::cpu.inst 1420 # number of overall MSHR hits
730system.cpu.icache.overall_mshr_hits::total 1420 # number of overall MSHR hits
731system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4104 # number of ReadReq MSHR misses
732system.cpu.icache.ReadReq_mshr_misses::total 4104 # number of ReadReq MSHR misses
733system.cpu.icache.demand_mshr_misses::cpu.inst 4104 # number of demand (read+write) MSHR misses
734system.cpu.icache.demand_mshr_misses::total 4104 # number of demand (read+write) MSHR misses
735system.cpu.icache.overall_mshr_misses::cpu.inst 4104 # number of overall MSHR misses
736system.cpu.icache.overall_mshr_misses::total 4104 # number of overall MSHR misses
737system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164891501 # number of ReadReq MSHR miss cycles
738system.cpu.icache.ReadReq_mshr_miss_latency::total 164891501 # number of ReadReq MSHR miss cycles
739system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164891501 # number of demand (read+write) MSHR miss cycles
740system.cpu.icache.demand_mshr_miss_latency::total 164891501 # number of demand (read+write) MSHR miss cycles
741system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164891501 # number of overall MSHR miss cycles
742system.cpu.icache.overall_mshr_miss_latency::total 164891501 # number of overall MSHR miss cycles
743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses
744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses
745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses
746system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses
747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses
748system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses
749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40178.240984 # average ReadReq mshr miss latency
750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40178.240984 # average ReadReq mshr miss latency
751system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency
752system.cpu.icache.demand_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency
753system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40178.240984 # average overall mshr miss latency
754system.cpu.icache.overall_avg_mshr_miss_latency::total 40178.240984 # average overall mshr miss latency
755system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
756system.cpu.l2cache.tags.replacements 0 # number of replacements
757system.cpu.l2cache.tags.tagsinuse 1935.733118 # Cycle average of tags in use
758system.cpu.l2cache.tags.total_refs 2084 # Total number of references to valid blocks.
759system.cpu.l2cache.tags.sampled_refs 2703 # Sample count of references to valid blocks.
760system.cpu.l2cache.tags.avg_refs 0.770995 # Average number of references to valid blocks.
761system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
762system.cpu.l2cache.tags.occ_blocks::writebacks 3.025142 # Average occupied blocks per requestor
763system.cpu.l2cache.tags.occ_blocks::cpu.inst 1410.130158 # Average occupied blocks per requestor
764system.cpu.l2cache.tags.occ_blocks::cpu.data 522.577818 # Average occupied blocks per requestor
765system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
766system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043034 # Average percentage of cache occupancy
767system.cpu.l2cache.tags.occ_percent::cpu.data 0.015948 # Average percentage of cache occupancy
768system.cpu.l2cache.tags.occ_percent::total 0.059074 # Average percentage of cache occupancy
769system.cpu.l2cache.tags.occ_task_id_blocks::1024 2703 # Occupied blocks per task id
770system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
771system.cpu.l2cache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
772system.cpu.l2cache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id
773system.cpu.l2cache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id
774system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1935 # Occupied blocks per task id
775system.cpu.l2cache.tags.occ_task_id_percent::1024 0.082489 # Percentage of cache occupancy per task id
776system.cpu.l2cache.tags.tag_accesses 51495 # Number of tag accesses
777system.cpu.l2cache.tags.data_accesses 51495 # Number of data accesses
778system.cpu.l2cache.ReadReq_hits::cpu.inst 2000 # number of ReadReq hits
779system.cpu.l2cache.ReadReq_hits::cpu.data 83 # number of ReadReq hits
780system.cpu.l2cache.ReadReq_hits::total 2083 # number of ReadReq hits
781system.cpu.l2cache.Writeback_hits::writebacks 17 # number of Writeback hits
782system.cpu.l2cache.Writeback_hits::total 17 # number of Writeback hits
783system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
784system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
785system.cpu.l2cache.ReadExReq_hits::cpu.data 12 # number of ReadExReq hits
786system.cpu.l2cache.ReadExReq_hits::total 12 # number of ReadExReq hits
787system.cpu.l2cache.demand_hits::cpu.inst 2000 # number of demand (read+write) hits
788system.cpu.l2cache.demand_hits::cpu.data 95 # number of demand (read+write) hits
789system.cpu.l2cache.demand_hits::total 2095 # number of demand (read+write) hits
790system.cpu.l2cache.overall_hits::cpu.inst 2000 # number of overall hits
791system.cpu.l2cache.overall_hits::cpu.data 95 # number of overall hits
792system.cpu.l2cache.overall_hits::total 2095 # number of overall hits
793system.cpu.l2cache.ReadReq_misses::cpu.inst 2043 # number of ReadReq misses
794system.cpu.l2cache.ReadReq_misses::cpu.data 672 # number of ReadReq misses
795system.cpu.l2cache.ReadReq_misses::total 2715 # number of ReadReq misses
796system.cpu.l2cache.UpgradeReq_misses::cpu.data 60 # number of UpgradeReq misses
797system.cpu.l2cache.UpgradeReq_misses::total 60 # number of UpgradeReq misses
798system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses
799system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses
800system.cpu.l2cache.demand_misses::cpu.inst 2043 # number of demand (read+write) misses
801system.cpu.l2cache.demand_misses::cpu.data 1747 # number of demand (read+write) misses
802system.cpu.l2cache.demand_misses::total 3790 # number of demand (read+write) misses
803system.cpu.l2cache.overall_misses::cpu.inst 2043 # number of overall misses
804system.cpu.l2cache.overall_misses::cpu.data 1747 # number of overall misses
805system.cpu.l2cache.overall_misses::total 3790 # number of overall misses
806system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 140715500 # number of ReadReq miss cycles
807system.cpu.l2cache.ReadReq_miss_latency::cpu.data 47433250 # number of ReadReq miss cycles
808system.cpu.l2cache.ReadReq_miss_latency::total 188148750 # number of ReadReq miss cycles
809system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 74164250 # number of ReadExReq miss cycles
810system.cpu.l2cache.ReadExReq_miss_latency::total 74164250 # number of ReadExReq miss cycles
811system.cpu.l2cache.demand_miss_latency::cpu.inst 140715500 # number of demand (read+write) miss cycles
812system.cpu.l2cache.demand_miss_latency::cpu.data 121597500 # number of demand (read+write) miss cycles
813system.cpu.l2cache.demand_miss_latency::total 262313000 # number of demand (read+write) miss cycles
814system.cpu.l2cache.overall_miss_latency::cpu.inst 140715500 # number of overall miss cycles
815system.cpu.l2cache.overall_miss_latency::cpu.data 121597500 # number of overall miss cycles
816system.cpu.l2cache.overall_miss_latency::total 262313000 # number of overall miss cycles
817system.cpu.l2cache.ReadReq_accesses::cpu.inst 4043 # number of ReadReq accesses(hits+misses)
818system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses)
819system.cpu.l2cache.ReadReq_accesses::total 4798 # number of ReadReq accesses(hits+misses)
820system.cpu.l2cache.Writeback_accesses::writebacks 17 # number of Writeback accesses(hits+misses)
821system.cpu.l2cache.Writeback_accesses::total 17 # number of Writeback accesses(hits+misses)
822system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses)
823system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses)
824system.cpu.l2cache.ReadExReq_accesses::cpu.data 1087 # number of ReadExReq accesses(hits+misses)
825system.cpu.l2cache.ReadExReq_accesses::total 1087 # number of ReadExReq accesses(hits+misses)
826system.cpu.l2cache.demand_accesses::cpu.inst 4043 # number of demand (read+write) accesses
827system.cpu.l2cache.demand_accesses::cpu.data 1842 # number of demand (read+write) accesses
828system.cpu.l2cache.demand_accesses::total 5885 # number of demand (read+write) accesses
829system.cpu.l2cache.overall_accesses::cpu.inst 4043 # number of overall (read+write) accesses
830system.cpu.l2cache.overall_accesses::cpu.data 1842 # number of overall (read+write) accesses
831system.cpu.l2cache.overall_accesses::total 5885 # number of overall (read+write) accesses
832system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.505318 # miss rate for ReadReq accesses
833system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890066 # miss rate for ReadReq accesses
834system.cpu.l2cache.ReadReq_miss_rate::total 0.565861 # miss rate for ReadReq accesses
835system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983607 # miss rate for UpgradeReq accesses
836system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983607 # miss rate for UpgradeReq accesses
837system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.988960 # miss rate for ReadExReq accesses
838system.cpu.l2cache.ReadExReq_miss_rate::total 0.988960 # miss rate for ReadExReq accesses
839system.cpu.l2cache.demand_miss_rate::cpu.inst 0.505318 # miss rate for demand accesses
840system.cpu.l2cache.demand_miss_rate::cpu.data 0.948426 # miss rate for demand accesses
841system.cpu.l2cache.demand_miss_rate::total 0.644010 # miss rate for demand accesses
842system.cpu.l2cache.overall_miss_rate::cpu.inst 0.505318 # miss rate for overall accesses
843system.cpu.l2cache.overall_miss_rate::cpu.data 0.948426 # miss rate for overall accesses
844system.cpu.l2cache.overall_miss_rate::total 0.644010 # miss rate for overall accesses
845system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68876.896721 # average ReadReq miss latency
846system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70585.193452 # average ReadReq miss latency
847system.cpu.l2cache.ReadReq_avg_miss_latency::total 69299.723757 # average ReadReq miss latency
848system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68990 # average ReadExReq miss latency
849system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68990 # average ReadExReq miss latency
850system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68876.896721 # average overall miss latency
851system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69603.606182 # average overall miss latency
852system.cpu.l2cache.demand_avg_miss_latency::total 69211.873351 # average overall miss latency
853system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68876.896721 # average overall miss latency
854system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69603.606182 # average overall miss latency
855system.cpu.l2cache.overall_avg_miss_latency::total 69211.873351 # average overall miss latency
856system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
857system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
858system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
859system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
860system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
861system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
862system.cpu.l2cache.fast_writes 0 # number of fast writes performed
863system.cpu.l2cache.cache_copies 0 # number of cache copies performed
864system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
865system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits
866system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits
867system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
868system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits
869system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
870system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
871system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits
872system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
873system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2040 # number of ReadReq MSHR misses
874system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 660 # number of ReadReq MSHR misses
875system.cpu.l2cache.ReadReq_mshr_misses::total 2700 # number of ReadReq MSHR misses
876system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 60 # number of UpgradeReq MSHR misses
877system.cpu.l2cache.UpgradeReq_mshr_misses::total 60 # number of UpgradeReq MSHR misses
878system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses
879system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses
880system.cpu.l2cache.demand_mshr_misses::cpu.inst 2040 # number of demand (read+write) MSHR misses
881system.cpu.l2cache.demand_mshr_misses::cpu.data 1735 # number of demand (read+write) MSHR misses
882system.cpu.l2cache.demand_mshr_misses::total 3775 # number of demand (read+write) MSHR misses
883system.cpu.l2cache.overall_mshr_misses::cpu.inst 2040 # number of overall MSHR misses
884system.cpu.l2cache.overall_mshr_misses::cpu.data 1735 # number of overall MSHR misses
885system.cpu.l2cache.overall_mshr_misses::total 3775 # number of overall MSHR misses
886system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114933000 # number of ReadReq MSHR miss cycles
887system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 38476250 # number of ReadReq MSHR miss cycles
888system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153409250 # number of ReadReq MSHR miss cycles
889system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 623553 # number of UpgradeReq MSHR miss cycles
890system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 623553 # number of UpgradeReq MSHR miss cycles
891system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60696250 # number of ReadExReq MSHR miss cycles
892system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60696250 # number of ReadExReq MSHR miss cycles
893system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114933000 # number of demand (read+write) MSHR miss cycles
894system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99172500 # number of demand (read+write) MSHR miss cycles
895system.cpu.l2cache.demand_mshr_miss_latency::total 214105500 # number of demand (read+write) MSHR miss cycles
896system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114933000 # number of overall MSHR miss cycles
897system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99172500 # number of overall MSHR miss cycles
898system.cpu.l2cache.overall_mshr_miss_latency::total 214105500 # number of overall MSHR miss cycles
899system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for ReadReq accesses
900system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.874172 # mshr miss rate for ReadReq accesses
901system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.562734 # mshr miss rate for ReadReq accesses
902system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983607 # mshr miss rate for UpgradeReq accesses
903system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983607 # mshr miss rate for UpgradeReq accesses
904system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.988960 # mshr miss rate for ReadExReq accesses
905system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.988960 # mshr miss rate for ReadExReq accesses
906system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for demand accesses
907system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for demand accesses
908system.cpu.l2cache.demand_mshr_miss_rate::total 0.641461 # mshr miss rate for demand accesses
909system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.504576 # mshr miss rate for overall accesses
910system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941911 # mshr miss rate for overall accesses
911system.cpu.l2cache.overall_mshr_miss_rate::total 0.641461 # mshr miss rate for overall accesses
912system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56339.705882 # average ReadReq mshr miss latency
913system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58297.348485 # average ReadReq mshr miss latency
914system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56818.240741 # average ReadReq mshr miss latency
915system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10392.550000 # average UpgradeReq mshr miss latency
916system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10392.550000 # average UpgradeReq mshr miss latency
917system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56461.627907 # average ReadExReq mshr miss latency
918system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56461.627907 # average ReadExReq mshr miss latency
919system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency
920system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency
921system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency
922system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56339.705882 # average overall mshr miss latency
923system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57159.942363 # average overall mshr miss latency
924system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56716.688742 # average overall mshr miss latency
925system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
926system.cpu.dcache.tags.replacements 56 # number of replacements
927system.cpu.dcache.tags.tagsinuse 1395.016190 # Cycle average of tags in use
928system.cpu.dcache.tags.total_refs 47368346 # Total number of references to valid blocks.
929system.cpu.dcache.tags.sampled_refs 1842 # Sample count of references to valid blocks.
930system.cpu.dcache.tags.avg_refs 25715.714441 # Average number of references to valid blocks.
931system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
932system.cpu.dcache.tags.occ_blocks::cpu.data 1395.016190 # Average occupied blocks per requestor
933system.cpu.dcache.tags.occ_percent::cpu.data 0.340580 # Average percentage of cache occupancy
934system.cpu.dcache.tags.occ_percent::total 0.340580 # Average percentage of cache occupancy
935system.cpu.dcache.tags.occ_task_id_blocks::1024 1786 # Occupied blocks per task id
936system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
937system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
938system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id
939system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
940system.cpu.dcache.tags.age_task_id_blocks_1024::4 1369 # Occupied blocks per task id
941system.cpu.dcache.tags.occ_task_id_percent::1024 0.436035 # Percentage of cache occupancy per task id
942system.cpu.dcache.tags.tag_accesses 94757994 # Number of tag accesses
943system.cpu.dcache.tags.data_accesses 94757994 # Number of data accesses
944system.cpu.dcache.ReadReq_hits::cpu.data 34966407 # number of ReadReq hits
945system.cpu.dcache.ReadReq_hits::total 34966407 # number of ReadReq hits
946system.cpu.dcache.WriteReq_hits::cpu.data 12356440 # number of WriteReq hits
947system.cpu.dcache.WriteReq_hits::total 12356440 # number of WriteReq hits
948system.cpu.dcache.SoftPFReq_hits::cpu.data 545 # number of SoftPFReq hits
949system.cpu.dcache.SoftPFReq_hits::total 545 # number of SoftPFReq hits
950system.cpu.dcache.LoadLockedReq_hits::cpu.data 22480 # number of LoadLockedReq hits
951system.cpu.dcache.LoadLockedReq_hits::total 22480 # number of LoadLockedReq hits
952system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
953system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
954system.cpu.dcache.demand_hits::cpu.data 47322847 # number of demand (read+write) hits
955system.cpu.dcache.demand_hits::total 47322847 # number of demand (read+write) hits
956system.cpu.dcache.overall_hits::cpu.data 47323392 # number of overall hits
957system.cpu.dcache.overall_hits::total 47323392 # number of overall hits
958system.cpu.dcache.ReadReq_misses::cpu.data 1942 # number of ReadReq misses
959system.cpu.dcache.ReadReq_misses::total 1942 # number of ReadReq misses
960system.cpu.dcache.WriteReq_misses::cpu.data 7847 # number of WriteReq misses
961system.cpu.dcache.WriteReq_misses::total 7847 # number of WriteReq misses
962system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
963system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
964system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
965system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
966system.cpu.dcache.demand_misses::cpu.data 9789 # number of demand (read+write) misses
967system.cpu.dcache.demand_misses::total 9789 # number of demand (read+write) misses
968system.cpu.dcache.overall_misses::cpu.data 9795 # number of overall misses
969system.cpu.dcache.overall_misses::total 9795 # number of overall misses
970system.cpu.dcache.ReadReq_miss_latency::cpu.data 120282480 # number of ReadReq miss cycles
971system.cpu.dcache.ReadReq_miss_latency::total 120282480 # number of ReadReq miss cycles
972system.cpu.dcache.WriteReq_miss_latency::cpu.data 504727051 # number of WriteReq miss cycles
973system.cpu.dcache.WriteReq_miss_latency::total 504727051 # number of WriteReq miss cycles
974system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 143500 # number of LoadLockedReq miss cycles
975system.cpu.dcache.LoadLockedReq_miss_latency::total 143500 # number of LoadLockedReq miss cycles
976system.cpu.dcache.demand_miss_latency::cpu.data 625009531 # number of demand (read+write) miss cycles
977system.cpu.dcache.demand_miss_latency::total 625009531 # number of demand (read+write) miss cycles
978system.cpu.dcache.overall_miss_latency::cpu.data 625009531 # number of overall miss cycles
979system.cpu.dcache.overall_miss_latency::total 625009531 # number of overall miss cycles
980system.cpu.dcache.ReadReq_accesses::cpu.data 34968349 # number of ReadReq accesses(hits+misses)
981system.cpu.dcache.ReadReq_accesses::total 34968349 # number of ReadReq accesses(hits+misses)
982system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
983system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
984system.cpu.dcache.SoftPFReq_accesses::cpu.data 551 # number of SoftPFReq accesses(hits+misses)
985system.cpu.dcache.SoftPFReq_accesses::total 551 # number of SoftPFReq accesses(hits+misses)
986system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22482 # number of LoadLockedReq accesses(hits+misses)
987system.cpu.dcache.LoadLockedReq_accesses::total 22482 # number of LoadLockedReq accesses(hits+misses)
988system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
989system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
990system.cpu.dcache.demand_accesses::cpu.data 47332636 # number of demand (read+write) accesses
991system.cpu.dcache.demand_accesses::total 47332636 # number of demand (read+write) accesses
992system.cpu.dcache.overall_accesses::cpu.data 47333187 # number of overall (read+write) accesses
993system.cpu.dcache.overall_accesses::total 47333187 # number of overall (read+write) accesses
994system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses
995system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses
996system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000635 # miss rate for WriteReq accesses
997system.cpu.dcache.WriteReq_miss_rate::total 0.000635 # miss rate for WriteReq accesses
998system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.010889 # miss rate for SoftPFReq accesses
999system.cpu.dcache.SoftPFReq_miss_rate::total 0.010889 # miss rate for SoftPFReq accesses
1000system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses
1001system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses
1002system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses
1003system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses
1004system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses
1005system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses
1006system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.425335 # average ReadReq miss latency
1007system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.425335 # average ReadReq miss latency
1008system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64321.020900 # average WriteReq miss latency
1009system.cpu.dcache.WriteReq_avg_miss_latency::total 64321.020900 # average WriteReq miss latency
1010system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71750 # average LoadLockedReq miss latency
1011system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71750 # average LoadLockedReq miss latency
1012system.cpu.dcache.demand_avg_miss_latency::cpu.data 63848.149045 # average overall miss latency
1013system.cpu.dcache.demand_avg_miss_latency::total 63848.149045 # average overall miss latency
1014system.cpu.dcache.overall_avg_miss_latency::cpu.data 63809.038387 # average overall miss latency
1015system.cpu.dcache.overall_avg_miss_latency::total 63809.038387 # average overall miss latency
1016system.cpu.dcache.blocked_cycles::no_mshrs 848 # number of cycles access was blocked
1017system.cpu.dcache.blocked_cycles::no_targets 85 # number of cycles access was blocked
1018system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked
1019system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
1020system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
1021system.cpu.dcache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked
1022system.cpu.dcache.fast_writes 0 # number of fast writes performed
1023system.cpu.dcache.cache_copies 0 # number of cache copies performed
1024system.cpu.dcache.writebacks::writebacks 17 # number of writebacks
1025system.cpu.dcache.writebacks::total 17 # number of writebacks
1026system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1189 # number of ReadReq MSHR hits
1027system.cpu.dcache.ReadReq_mshr_hits::total 1189 # number of ReadReq MSHR hits
1028system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6701 # number of WriteReq MSHR hits
1029system.cpu.dcache.WriteReq_mshr_hits::total 6701 # number of WriteReq MSHR hits
1030system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
1031system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
1032system.cpu.dcache.demand_mshr_hits::cpu.data 7890 # number of demand (read+write) MSHR hits
1033system.cpu.dcache.demand_mshr_hits::total 7890 # number of demand (read+write) MSHR hits
1034system.cpu.dcache.overall_mshr_hits::cpu.data 7890 # number of overall MSHR hits
1035system.cpu.dcache.overall_mshr_hits::total 7890 # number of overall MSHR hits
1036system.cpu.dcache.ReadReq_mshr_misses::cpu.data 753 # number of ReadReq MSHR misses
1037system.cpu.dcache.ReadReq_mshr_misses::total 753 # number of ReadReq MSHR misses
1038system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1146 # number of WriteReq MSHR misses
1039system.cpu.dcache.WriteReq_mshr_misses::total 1146 # number of WriteReq MSHR misses
1040system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
1041system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
1042system.cpu.dcache.demand_mshr_misses::cpu.data 1899 # number of demand (read+write) MSHR misses
1043system.cpu.dcache.demand_mshr_misses::total 1899 # number of demand (read+write) MSHR misses
1044system.cpu.dcache.overall_mshr_misses::cpu.data 1903 # number of overall MSHR misses
1045system.cpu.dcache.overall_mshr_misses::total 1903 # number of overall MSHR misses
1046system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48859513 # number of ReadReq MSHR miss cycles
1047system.cpu.dcache.ReadReq_mshr_miss_latency::total 48859513 # number of ReadReq MSHR miss cycles
1048system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76658945 # number of WriteReq MSHR miss cycles
1049system.cpu.dcache.WriteReq_mshr_miss_latency::total 76658945 # number of WriteReq MSHR miss cycles
1050system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 305000 # number of SoftPFReq MSHR miss cycles
1051system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 305000 # number of SoftPFReq MSHR miss cycles
1052system.cpu.dcache.demand_mshr_miss_latency::cpu.data 125518458 # number of demand (read+write) MSHR miss cycles
1053system.cpu.dcache.demand_mshr_miss_latency::total 125518458 # number of demand (read+write) MSHR miss cycles
1054system.cpu.dcache.overall_mshr_miss_latency::cpu.data 125823458 # number of overall MSHR miss cycles
1055system.cpu.dcache.overall_mshr_miss_latency::total 125823458 # number of overall MSHR miss cycles
1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000093 # mshr miss rate for WriteReq accesses
1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000093 # mshr miss rate for WriteReq accesses
1060system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007260 # mshr miss rate for SoftPFReq accesses
1061system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007260 # mshr miss rate for SoftPFReq accesses
1062system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
1063system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
1064system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
1065system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64886.471448 # average ReadReq mshr miss latency
1067system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64886.471448 # average ReadReq mshr miss latency
1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66892.622164 # average WriteReq mshr miss latency
1069system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66892.622164 # average WriteReq mshr miss latency
1070system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76250 # average SoftPFReq mshr miss latency
1071system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76250 # average SoftPFReq mshr miss latency
1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66097.134281 # average overall mshr miss latency
1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 66097.134281 # average overall mshr miss latency
1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66118.475039 # average overall mshr miss latency
1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 66118.475039 # average overall mshr miss latency
1076system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1077
1078---------- End Simulation Statistics ----------