Cross Reference: /gem5/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.130383 # Number of seconds simulated 4sim_ticks 130382890500 # Number of ticks simulated 5final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.130383 # Number of seconds simulated 4sim_ticks 130382890500 # Number of ticks simulated 5final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 181123 # Simulator instruction rate (inst/s) 8host_op_rate 190933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 137045131 # Simulator tick rate (ticks/s) 10host_mem_usage 270196 # Number of bytes of host memory used 11host_seconds 951.39 # Real time elapsed on the host	7host_inst_rate 369340 # Simulator instruction rate (inst/s) 8host_op_rate 389344 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 279457902 # Simulator tick rate (ticks/s) 10host_mem_usage 317800 # Number of bytes of host memory used 11host_seconds 466.56 # Real time elapsed on the host
12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 247424 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.803682 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 19system.physmem.bytes_read::total 247424 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) 248system.physmem_1.averagePower 668.803682 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states 250system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	254system.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
253system.cpu.branchPred.lookups 49622074 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks	255system.cpu.branchPred.lookups 49622074 # Number of BP lookups 256system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks
	269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses	300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses
	329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 400 # Number of system calls	360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 400 # Number of system calls
	390system.cpu.pwrStateResidencyTicks::ON 130382890500 # Cumulative time (in ticks) in various power states
384system.cpu.numCycles 260765781 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.committedInsts 172317810 # Number of instructions committed 388system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 389system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit 390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 391system.cpu.cpi 1.513284 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 422system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 423system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 424system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction 425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 427system.cpu.op_class_0::total 181650743 # Class of committed instruction 428system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked 429system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped	391system.cpu.numCycles 260765781 # number of cpu cycles simulated 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 172317810 # Number of instructions committed 395system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 396system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 398system.cpu.cpi 1.513284 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 429system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 430system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 181650743 # Class of committed instruction 435system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped
	437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
430system.cpu.dcache.tags.replacements 42 # number of replacements 431system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use 432system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. 433system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. 434system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. 435system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor 437system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id 445system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id 446system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses 447system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses	438system.cpu.dcache.tags.replacements 42 # number of replacements 439system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy 447system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id 453system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id 454system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses 455system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses
	456system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
448system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits 449system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits 450system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits 451system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits 452system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 453system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 454system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 455system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency 561system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency 562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 563system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency 564system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency 565system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency 566system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency 567system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency	457system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits 458system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits 459system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits 460system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits 461system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 462system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 463system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 464system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 569system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency 570system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency 571system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 572system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency 573system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency 574system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency 575system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency 576system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
	577system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
568system.cpu.icache.tags.replacements 2881 # number of replacements 569system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use 570system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. 571system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. 572system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. 573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 574system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor 575system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy 576system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy 577system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 579system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 580system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id 581system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id 582system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id 583system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id 584system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses 585system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses	578system.cpu.icache.tags.replacements 2881 # number of replacements 579system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use 580system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. 581system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. 582system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. 583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 584system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor 585system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy 586system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy 587system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 590system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id 591system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id 592system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id 593system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id 594system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses 595system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses
	596system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
586system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits 587system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits 588system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits 589system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits 590system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits 591system.cpu.icache.overall_hits::total 70779397 # number of overall hits 592system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses 593system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 646system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 647system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 648system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency 649system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency 650system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 651system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency 652system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 653system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency	597system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits 598system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits 599system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits 600system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits 601system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits 602system.cpu.icache.overall_hits::total 70779397 # number of overall hits 603system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses 604system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 658system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency 660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 662system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 664system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
	665system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
654system.cpu.l2cache.tags.replacements 0 # number of replacements 655system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use 656system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. 657system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. 658system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. 659system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 660system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 668system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 669system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 670system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 671system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id 672system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id 673system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id 674system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses 675system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses	666system.cpu.l2cache.tags.replacements 0 # number of replacements 667system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use 668system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. 669system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. 670system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. 671system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 672system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor 673system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 680system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 681system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 682system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 683system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id 684system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id 685system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id 686system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses 687system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses
	688system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
676system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 677system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 678system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits 679system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits 680system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 681system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 682system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits 683system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits --- 134 unchanged lines hidden (view full) --- 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency 820system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. 821system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. 822system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 823system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 824system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 825system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	689system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 690system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 691system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits 692system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits 693system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 694system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 695system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits 696system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits --- 134 unchanged lines hidden (view full) --- 831system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 832system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency 833system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. 834system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. 835system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 836system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 837system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 838system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	839system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
826system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution 829system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution 830system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution 832system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 850system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 851system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram 852system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) 853system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 854system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) 855system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 856system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) 857system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)	840system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution 845system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution 846system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution 847system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 864system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 865system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram 866system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) 867system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 868system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) 869system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 870system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) 871system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
	872system.membus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states
858system.membus.trans_dist::ReadResp 2775 # Transaction distribution 859system.membus.trans_dist::ReadExReq 1091 # Transaction distribution 860system.membus.trans_dist::ReadExResp 1091 # Transaction distribution 861system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution 862system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) 863system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) 864system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) 865system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---	873system.membus.trans_dist::ReadResp 2775 # Transaction distribution 874system.membus.trans_dist::ReadExReq 1091 # Transaction distribution 875system.membus.trans_dist::ReadExResp 1091 # Transaction distribution 876system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution 877system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) 878system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) 879system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) 880system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.130383 # Number of seconds simulated
4sim_ticks 130382890500 # Number of ticks simulated
5final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 181123 # Simulator instruction rate (inst/s)
8host_op_rate 190933 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 137045131 # Simulator tick rate (ticks/s)
10host_mem_usage 270196 # Number of bytes of host memory used
11host_seconds 951.39 # Real time elapsed on the host

7host_inst_rate 369340 # Simulator instruction rate (inst/s)
8host_op_rate 389344 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 279457902 # Simulator tick rate (ticks/s)
10host_mem_usage 317800 # Number of bytes of host memory used
11host_seconds 466.56 # Real time elapsed on the host

12sim_insts 172317810 # Number of instructions simulated
13sim_ops 181650743 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
18system.physmem.bytes_read::total 247424 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory

--- 221 unchanged lines hidden (view full) ---

245system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ)
247system.physmem_1.averagePower 668.803682 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states
249system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
19system.physmem.bytes_read::total 247424 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory

--- 221 unchanged lines hidden (view full) ---

246system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ)
247system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ)
248system.physmem_1.averagePower 668.803682 # Core power per rank (mW)
249system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states
250system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states
251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
252system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states
253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

254system.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

253system.cpu.branchPred.lookups 49622074 # Number of BP lookups
254system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
262system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups.
263system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits.
264system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses.
265system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches.
266system.cpu_clk_domain.clock 500 # Clock period in ticks

255system.cpu.branchPred.lookups 49622074 # Number of BP lookups
256system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted
257system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect
258system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups
259system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits
260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
261system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage
262system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target.
263system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
264system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups.
265system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits.
266system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses.
267system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches.
268system.cpu_clk_domain.clock 500 # Clock period in ticks

269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

296system.cpu.dtb.walker.walks 0 # Table walker walks requested
297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dtb.read_accesses 0 # DTB read accesses
320system.cpu.dtb.write_accesses 0 # DTB write accesses
321system.cpu.dtb.inst_accesses 0 # ITB inst accesses
322system.cpu.dtb.hits 0 # DTB hits
323system.cpu.dtb.misses 0 # DTB misses
324system.cpu.dtb.accesses 0 # DTB accesses

300system.cpu.dtb.walker.walks 0 # Table walker walks requested
301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
323system.cpu.dtb.read_accesses 0 # DTB read accesses
324system.cpu.dtb.write_accesses 0 # DTB write accesses
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
326system.cpu.dtb.hits 0 # DTB hits
327system.cpu.dtb.misses 0 # DTB misses
328system.cpu.dtb.accesses 0 # DTB accesses

329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

354system.cpu.itb.walker.walks 0 # Table walker walks requested
355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.itb.read_accesses 0 # DTB read accesses
378system.cpu.itb.write_accesses 0 # DTB write accesses
379system.cpu.itb.inst_accesses 0 # ITB inst accesses
380system.cpu.itb.hits 0 # DTB hits
381system.cpu.itb.misses 0 # DTB misses
382system.cpu.itb.accesses 0 # DTB accesses
383system.cpu.workload.num_syscalls 400 # Number of system calls

360system.cpu.itb.walker.walks 0 # Table walker walks requested
361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
383system.cpu.itb.read_accesses 0 # DTB read accesses
384system.cpu.itb.write_accesses 0 # DTB write accesses
385system.cpu.itb.inst_accesses 0 # ITB inst accesses
386system.cpu.itb.hits 0 # DTB hits
387system.cpu.itb.misses 0 # DTB misses
388system.cpu.itb.accesses 0 # DTB accesses
389system.cpu.workload.num_syscalls 400 # Number of system calls

390system.cpu.pwrStateResidencyTicks::ON 130382890500 # Cumulative time (in ticks) in various power states

384system.cpu.numCycles 260765781 # number of cpu cycles simulated
385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
387system.cpu.committedInsts 172317810 # Number of instructions committed
388system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
389system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit
390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
391system.cpu.cpi 1.513284 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

422system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
423system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
424system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
427system.cpu.op_class_0::total 181650743 # Class of committed instruction
428system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
429system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped

391system.cpu.numCycles 260765781 # number of cpu cycles simulated
392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
394system.cpu.committedInsts 172317810 # Number of instructions committed
395system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
396system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit
397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
398system.cpu.cpi 1.513284 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

429system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
430system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
431system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
434system.cpu.op_class_0::total 181650743 # Class of committed instruction
435system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
436system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped

437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

430system.cpu.dcache.tags.replacements 42 # number of replacements
431system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
432system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
433system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
434system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks.
435system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
436system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor
437system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy
438system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy
439system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
440system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
441system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
442system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
443system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
444system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
445system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
446system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
447system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses

438system.cpu.dcache.tags.replacements 42 # number of replacements
439system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
440system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
441system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
442system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks.
443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
444system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor
445system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy
446system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy
447system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
448system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
449system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
450system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
451system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
452system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
453system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
454system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
455system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses

456system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

448system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
449system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
450system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
451system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits
452system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
453system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
454system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
455system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency
561system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency
562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
563system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
564system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency
565system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
566system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
567system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency

457system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
458system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
459system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
460system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits
461system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
462system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
463system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
464system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

569system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency
570system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency
571system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
572system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
573system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency
574system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
575system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
576system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency

577system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

568system.cpu.icache.tags.replacements 2881 # number of replacements
569system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
570system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
571system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks.
572system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks.
573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
574system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor
575system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy
576system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy
577system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
578system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
579system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
580system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
581system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
582system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
583system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
584system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
585system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses

578system.cpu.icache.tags.replacements 2881 # number of replacements
579system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
580system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
581system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks.
582system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks.
583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
584system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor
585system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy
586system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy
587system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
588system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
589system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
590system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
591system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
592system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
593system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
594system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
595system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses

596system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

586system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
587system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
588system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
589system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits
590system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits
591system.cpu.icache.overall_hits::total 70779397 # number of overall hits
592system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses
593system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

646system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
647system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
648system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency
649system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency
650system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
651system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
652system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
653system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency

597system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
598system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
599system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
600system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits
601system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits
602system.cpu.icache.overall_hits::total 70779397 # number of overall hits
603system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses
604system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
658system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency
660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency
661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
662system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
664system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency

665system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

654system.cpu.l2cache.tags.replacements 0 # number of replacements
655system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
656system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
657system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks.
658system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks.
659system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
660system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor
661system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor

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668system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
669system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
670system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
671system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
672system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id
673system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
674system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
675system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses

666system.cpu.l2cache.tags.replacements 0 # number of replacements
667system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
668system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
669system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks.
670system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks.
671system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
672system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor
673system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

680system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
681system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
682system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
683system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
684system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id
685system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
686system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
687system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses

688system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

676system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
677system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
678system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
679system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits
680system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
681system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
682system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits
683system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits

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818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
819system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
820system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
821system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
822system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
823system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
824system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
825system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

689system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
690system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
691system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
692system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits
693system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
694system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
695system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits
696system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits

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831system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
832system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
833system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
834system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
835system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
836system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
837system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
838system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

839system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states

826system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
827system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
828system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
829system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
830system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
831system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
832system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution
833system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution

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850system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
851system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram
852system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks)
853system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
854system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks)
855system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
856system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks)
857system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

840system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
841system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
842system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
843system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
844system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
845system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
846system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution
847system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution

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864system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
865system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram
866system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks)
867system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
868system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks)
869system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
870system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks)
871system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

872system.membus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states