| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.130383 # Number of seconds simulated 4sim_ticks 130382890500 # Number of ticks simulated 5final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.130383 # Number of seconds simulated 4sim_ticks 130382890500 # Number of ticks simulated 5final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 248644 # Simulator instruction rate (inst/s) 8host_op_rate 262111 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 188134778 # Simulator tick rate (ticks/s) 10host_mem_usage 275596 # Number of bytes of host memory used 11host_seconds 693.03 # Real time elapsed on the host | 7host_inst_rate 248771 # Simulator instruction rate (inst/s) 8host_op_rate 262245 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 188230845 # Simulator tick rate (ticks/s) 10host_mem_usage 275588 # Number of bytes of host memory used 11host_seconds 692.68 # Real time elapsed on the host |
| 12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 247424 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory --- 490 unchanged lines hidden (view full) --- 510system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 247424 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory --- 490 unchanged lines hidden (view full) --- 510system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 518system.cpu.dcache.fast_writes 0 # number of fast writes performed 519system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 520system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 521system.cpu.dcache.writebacks::total 16 # number of writebacks 522system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits 523system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 524system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits 526system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits 527system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 562system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency 564system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency 566system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency 568system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency | 518system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 519system.cpu.dcache.writebacks::total 16 # number of writebacks 520system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits 521system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 522system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 523system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits 524system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits 525system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency 561system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency 562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 563system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency 564system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency 565system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency 566system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency 567system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency |
| 570system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 571system.cpu.icache.tags.replacements 2881 # number of replacements 572system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use 573system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. 574system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. 575system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. 576system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 577system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor 578system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 623system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency 625system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 626system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 627system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 629system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 630system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 568system.cpu.icache.tags.replacements 2881 # number of replacements 569system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use 570system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. 571system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. 572system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. 573system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 574system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor 575system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 620system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency 621system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency 622system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 623system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 625system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 627system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 631system.cpu.icache.fast_writes 0 # number of fast writes performed 632system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 633system.cpu.icache.writebacks::writebacks 2881 # number of writebacks 634system.cpu.icache.writebacks::total 2881 # number of writebacks 635system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses 636system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses 637system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses 638system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses 639system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses 640system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 651system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 652system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 653system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency 654system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency 655system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 656system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency 657system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 658system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency | 628system.cpu.icache.writebacks::writebacks 2881 # number of writebacks 629system.cpu.icache.writebacks::total 2881 # number of writebacks 630system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses 631system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses 632system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses 633system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses 634system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses 635system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 646system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 647system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 648system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency 649system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency 650system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 651system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency 652system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 653system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency |
| 659system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 660system.cpu.l2cache.tags.replacements 0 # number of replacements 661system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use 662system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. 663system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. 664system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. 665system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 666system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 760system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency 762system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 654system.cpu.l2cache.tags.replacements 0 # number of replacements 655system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use 656system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. 657system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. 658system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. 659system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 660system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 754system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency 755system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency 756system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 768system.cpu.l2cache.fast_writes 0 # number of fast writes performed 769system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 770system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 771system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 772system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 773system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 774system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 775system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 776system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 777system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits --- 42 unchanged lines hidden (view full) --- 820system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency 821system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency 822system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency 823system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency 825system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency 826system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency | 762system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 763system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 764system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 765system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 766system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 767system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 768system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 769system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits --- 42 unchanged lines hidden (view full) --- 812system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency 813system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency 814system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency 817system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency |
| 828system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 829system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. 830system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. 831system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 832system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 833system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 834system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 835system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 836system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution --- 55 unchanged lines hidden --- | 820system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. 821system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. 822system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 823system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 824system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 825system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 826system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution --- 55 unchanged lines hidden --- |