| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.130773 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.130773 # Number of seconds simulated |
| 4sim_ticks 130772636500 # Number of ticks simulated 5final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 130772642500 # Number of ticks simulated 5final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 167747 # Simulator instruction rate (inst/s) 8host_op_rate 176832 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 127303889 # Simulator tick rate (ticks/s) 10host_mem_usage 312696 # Number of bytes of host memory used 11host_seconds 1027.25 # Real time elapsed on the host | 7host_inst_rate 233615 # Simulator instruction rate (inst/s) 8host_op_rate 246267 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 177290947 # Simulator tick rate (ticks/s) 10host_mem_usage 321196 # Number of bytes of host memory used 11host_seconds 737.62 # Real time elapsed on the host |
| 12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 247424 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) | 12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 18system.physmem.bytes_read::total 247424 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) |
| 25system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s) | 25system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) |
| 26system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) | 26system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s) | 30system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) |
| 31system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3866 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM --- 31 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 31system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3866 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM --- 31 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 130772543000 # Total gap between requests | 78system.physmem.totGap 130772548000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 3866 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 3866 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 91 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation | 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 91 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation |
| 203system.physmem.totQLat 28055750 # Total ticks spent queuing 204system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 27654500 # Total ticks spent queuing 204system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 2957 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 209system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 2957 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 33826317.38 # Average gap between requests | 223system.physmem.avgGap 33826318.68 # Average gap between requests |
| 224system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) | 224system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) |
| 230system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.826718 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states | 230system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.826558 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states |
| 235system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) |
| 244system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.811822 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states | 244system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.811714 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 49732170 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage --- 112 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 49732170 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage --- 112 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls |
| 380system.cpu.numCycles 261545273 # number of cpu cycles simulated | 380system.cpu.numCycles 261545285 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317810 # Number of instructions committed 384system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 387system.cpu.cpi 1.517808 # CPI: cycles per instruction 388system.cpu.ipc 0.658845 # IPC: instructions per cycle | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317810 # Number of instructions committed 384system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 387system.cpu.cpi 1.517808 # CPI: cycles per instruction 388system.cpu.ipc 0.658845 # IPC: instructions per cycle |
| 389system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped | 389system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 42 # number of replacements | 391system.cpu.dcache.tags.replacements 42 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use | 392system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use |
| 393system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 393system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor | 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor |
| 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id --- 19 unchanged lines hidden (view full) --- 425system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses 427system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 429system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses 432system.cpu.dcache.overall_misses::total 2443 # number of overall misses | 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id --- 19 unchanged lines hidden (view full) --- 425system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses 427system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 429system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses 432system.cpu.dcache.overall_misses::total 2443 # number of overall misses |
| 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles | 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles |
| 441system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) 443system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses | 441system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) 443system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses |
| 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency | 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency |
| 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses | 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses |
| 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles | 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles |
| 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles | 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles |
| 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles | 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles |
| 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses | 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses |
| 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency | 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency |
| 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency | 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency |
| 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency | 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency |
| 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu.icache.tags.replacements 2888 # number of replacements | 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 532system.cpu.icache.tags.replacements 2888 # number of replacements |
| 533system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use | 533system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use |
| 534system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. 535system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. 536system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 534system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. 535system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. 536system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 538system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor | 538system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor |
| 539system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy 541system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 544system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 554system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits 555system.cpu.icache.overall_hits::total 71011798 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses 561system.cpu.icache.overall_misses::total 4685 # number of overall misses | 539system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy 541system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 544system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 554system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits 555system.cpu.icache.overall_hits::total 71011798 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses 561system.cpu.icache.overall_misses::total 4685 # number of overall misses |
| 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles | 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles |
| 568system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses | 568system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses |
| 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency | 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency |
| 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses | 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses |
| 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles | 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles |
| 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses | 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses |
| 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency | 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency |
| 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements | 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 620system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use | 620system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use |
| 621system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks. 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 621system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks. 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 625system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor | 625system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor |
| 628system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.061054 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 2784 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id --- 23 unchanged lines hidden (view full) --- 659system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses 660system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses 661system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses 662system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses 663system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses 664system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses 665system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses 666system.cpu.l2cache.overall_misses::total 3883 # number of overall misses | 628system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.061054 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 2784 # Occupied blocks per task id 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id --- 23 unchanged lines hidden (view full) --- 659system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses 660system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses 661system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses 662system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses 663system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses 664system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses 665system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses 666system.cpu.l2cache.overall_misses::total 3883 # number of overall misses |
| 667system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles 670system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles 671system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles 672system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles 673system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles 674system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles 675system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles 676system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles 678system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles | 667system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles 670system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles 671system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles 672system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles 673system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles 674system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles 675system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles 676system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles 678system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles |
| 679system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 683system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) 684system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses) 685system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) 686system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses 698system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461259 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.597844 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses | 679system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 683system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) 684system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses) 685system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) 686system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses 698system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461259 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.597844 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses |
| 705system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency 706system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency 707system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency 708system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency 709system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency 710system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency 713system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency | 705system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency 706system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency 707system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency 708system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency 709system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency 710system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency 713system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency |
| 717system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.l2cache.fast_writes 0 # number of fast writes performed 724system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 739system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses 740system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses 741system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses 746system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses | 717system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.l2cache.fast_writes 0 # number of fast writes performed 724system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 14 unchanged lines hidden (view full) --- 739system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses 740system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses 741system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses 742system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses 743system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses 745system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses 746system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses |
| 747system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles 748system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles 749system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles 750system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles 751system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles 752system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles | 747system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles 748system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles 749system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles 750system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles 751system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles 752system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles 753system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles |
| 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 761system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses 762system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses 763system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses 764system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses | 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 761system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses 762system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses 763system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses 764system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses |
| 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency 773system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency 774system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency 775system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency 776system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency | 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency 773system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency 774system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency 775system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency 776system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency |
| 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 784system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. 785system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. 786system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 787system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 788system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 789system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 784system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution 785system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 786system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution 787system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 788system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 789system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution 790system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution 791system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) 792system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) 793system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) 794system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299776 # Cumulative packet size per connected master and slave (bytes) 795system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) 796system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) 797system.cpu.toL2Bus.snoops 0 # Total snoops (count) 798system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram | 790system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution 791system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 792system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution 793system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 794system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 795system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution 796system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution 797system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) 798system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) 799system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) 800system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299776 # Cumulative packet size per connected master and slave (bytes) 801system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) 802system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) 803system.cpu.toL2Bus.snoops 0 # Total snoops (count) 804system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram |
| 799system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 800system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 805system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram 806system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram |
| 801system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 807system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 802system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 803system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram | 808system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram 809system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram |
| 804system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 805system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 810system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 811system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 806system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 812system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 807system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 808system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram 809system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) 810system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 811system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) 812system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 813system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) 814system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 826system.membus.snoop_fanout::stdev 0 # Request fanout histogram 827system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 828system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram 829system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 830system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 831system.membus.snoop_fanout::min_value 0 # Request fanout histogram 832system.membus.snoop_fanout::max_value 0 # Request fanout histogram 833system.membus.snoop_fanout::total 3866 # Request fanout histogram | 813system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 814system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram 815system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) 816system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 817system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) 818system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 819system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) 820system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 832system.membus.snoop_fanout::stdev 0 # Request fanout histogram 833system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 834system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram 835system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 836system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 837system.membus.snoop_fanout::min_value 0 # Request fanout histogram 838system.membus.snoop_fanout::max_value 0 # Request fanout histogram 839system.membus.snoop_fanout::total 3866 # Request fanout histogram |
| 834system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks) | 840system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) |
| 835system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 841system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 836system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks) | 842system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) |
| 837system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 838 839---------- End Simulation Statistics ---------- | 843system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 844 845---------- End Simulation Statistics ---------- |