| stats.txt (10827:7f5467f2f8b8) | stats.txt (10852:5b58b4cccfd7) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.131767 # Number of seconds simulated 4sim_ticks 131767151500 # Number of ticks simulated 5final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.131586 # Number of seconds simulated 4sim_ticks 131586268500 # Number of ticks simulated 5final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 244794 # Simulator instruction rate (inst/s) 8host_op_rate 258052 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 187187675 # Simulator tick rate (ticks/s) 10host_mem_usage 317932 # Number of bytes of host memory used 11host_seconds 703.93 # Real time elapsed on the host | 7host_inst_rate 246297 # Simulator instruction rate (inst/s) 8host_op_rate 259636 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 188078312 # Simulator tick rate (ticks/s) 10host_mem_usage 317920 # Number of bytes of host memory used 11host_seconds 699.64 # Real time elapsed on the host |
| 12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172317810 # Number of instructions simulated 13sim_ops 181650743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 138368 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 247616 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 247680 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138368 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138368 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory | 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3869 # Number of read requests accepted | 23system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3870 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 247680 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 247680 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 305 # Per bank write bursts 45system.physmem.perBankRdBursts::1 217 # Per bank write bursts 46system.physmem.perBankRdBursts::2 135 # Per bank write bursts 47system.physmem.perBankRdBursts::3 313 # Per bank write bursts | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 305 # Per bank write bursts 45system.physmem.perBankRdBursts::1 217 # Per bank write bursts 46system.physmem.perBankRdBursts::2 135 # Per bank write bursts 47system.physmem.perBankRdBursts::3 313 # Per bank write bursts |
| 48system.physmem.perBankRdBursts::4 307 # Per bank write bursts | 48system.physmem.perBankRdBursts::4 308 # Per bank write bursts |
| 49system.physmem.perBankRdBursts::5 305 # Per bank write bursts 50system.physmem.perBankRdBursts::6 273 # Per bank write bursts 51system.physmem.perBankRdBursts::7 222 # Per bank write bursts 52system.physmem.perBankRdBursts::8 249 # Per bank write bursts 53system.physmem.perBankRdBursts::9 218 # Per bank write bursts 54system.physmem.perBankRdBursts::10 295 # Per bank write bursts | 49system.physmem.perBankRdBursts::5 305 # Per bank write bursts 50system.physmem.perBankRdBursts::6 273 # Per bank write bursts 51system.physmem.perBankRdBursts::7 222 # Per bank write bursts 52system.physmem.perBankRdBursts::8 249 # Per bank write bursts 53system.physmem.perBankRdBursts::9 218 # Per bank write bursts 54system.physmem.perBankRdBursts::10 295 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::11 200 # Per bank write bursts | 55system.physmem.perBankRdBursts::11 201 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::12 183 # Per bank write bursts 57system.physmem.perBankRdBursts::13 218 # Per bank write bursts 58system.physmem.perBankRdBursts::14 224 # Per bank write bursts | 56system.physmem.perBankRdBursts::12 183 # Per bank write bursts 57system.physmem.perBankRdBursts::13 218 # Per bank write bursts 58system.physmem.perBankRdBursts::14 224 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::15 205 # Per bank write bursts | 59system.physmem.perBankRdBursts::15 204 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 131767057000 # Total gap between requests | 78system.physmem.totGap 131586174000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 3869 # Read request sizes (log2) | 85system.physmem.readPktSize::6 3870 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation 203system.physmem.totQLat 28218000 # Total ticks spent queuing 204system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation 203system.physmem.totQLat 26462250 # Total ticks spent queuing 204system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 209system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 2961 # Number of row buffer hits during reads | 219system.physmem.readRowHits 2963 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 34057135.44 # Average gap between requests 224system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 34001595.35 # Average gap between requests 224system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.827838 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states | 229system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.824061 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states |
| 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.799395 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states | 243system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.792204 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 49934214 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits | 253system.cpu.branchPred.lookups 49889699 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target. | 259system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target. |
| 261system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls | 261system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls |
| 380system.cpu.numCycles 263534303 # number of cpu cycles simulated | 380system.cpu.numCycles 263172537 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317810 # Number of instructions committed 384system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317810 # Number of instructions committed 384system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed |
| 385system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit | 385system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit |
| 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 387system.cpu.cpi 1.529350 # CPI: cycles per instruction 388system.cpu.ipc 0.653872 # IPC: instructions per cycle 389system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 1.527251 # CPI: cycles per instruction 388system.cpu.ipc 0.654771 # IPC: instructions per cycle 389system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 42 # number of replacements | 391system.cpu.dcache.tags.replacements 42 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks. | 392system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks. |
| 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. | 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. |
| 395system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks. | 395system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks. |
| 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy | 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy |
| 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id | 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id |
| 407system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits | 407system.cpu.dcache.tags.tag_accesses 81594514 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits |
| 411system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits 413system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits 414system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits 415system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 416system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 417system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 418system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 411system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits 413system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits 414system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits 415system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 416system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 417system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 418system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 419system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits 422system.cpu.dcache.overall_hits::total 40719565 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses | 419system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits 422system.cpu.dcache.overall_hits::total 40749098 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses |
| 425system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses 427system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses | 425system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses 427system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 428system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses |
| 429system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses 432system.cpu.dcache.overall_misses::total 2438 # number of overall misses 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles 441system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses) | 429system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses 430system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses 431system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses 432system.cpu.dcache.overall_misses::total 2440 # number of overall misses 433system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles 434system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles 437system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles 438system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles 439system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles 440system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles 441system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses) |
| 443system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 465 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 443system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::total 465 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 451system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses 452system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses 453system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses 454system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses | 451system.cpu.dcache.demand_accesses::cpu.data 40751073 # number of demand (read+write) accesses 452system.cpu.dcache.demand_accesses::total 40751073 # number of demand (read+write) accesses 453system.cpu.dcache.overall_accesses::cpu.data 40751538 # number of overall (read+write) accesses 454system.cpu.dcache.overall_accesses::total 40751538 # number of overall (read+write) accesses |
| 455system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses 456system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002151 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.002151 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses | 455system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses 456system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses 457system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 458system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 459system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002151 # miss rate for SoftPFReq accesses 460system.cpu.dcache.SoftPFReq_miss_rate::total 0.002151 # miss rate for SoftPFReq accesses 461system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 462system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 464system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses |
| 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency | 465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency 466system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency 467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency 469system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency 470system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency |
| 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 482system.cpu.dcache.writebacks::total 16 # number of writebacks | 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 482system.cpu.dcache.writebacks::total 16 # number of writebacks |
| 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits | 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits |
| 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits | 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits |
| 487system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits 488system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits 489system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits 490system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits | 487system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits 488system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits 489system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits 490system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits |
| 491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses 492system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses | 491system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses 492system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 493system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 495system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 496system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses |
| 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85210500 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles | 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles |
| 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles | 505system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles 506system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles |
| 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles | 507system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles 508system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles 509system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles 510system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles |
| 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002151 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses | 511system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002151 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 518system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 519system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 520system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses |
| 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency | 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency |
| 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency | 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency |
| 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency | 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency |
| 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 531system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 532system.cpu.icache.tags.replacements 2892 # number of replacements 533system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use 534system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks. 535system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks. 536system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks. | 532system.cpu.icache.tags.replacements 2889 # number of replacements 533system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use 534system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks. 535system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks. 536system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks. |
| 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 537system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 538system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor 539system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy | 538system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor 539system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy 540system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy |
| 541system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id | 541system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id 542system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 543system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id |
| 544system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id | 544system.cpu.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id 545system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id |
| 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id 547system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id | 546system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id 547system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id |
| 548system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses 549system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses 550system.cpu.icache.ReadReq_hits::cpu.inst 71598587 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 71598587 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 71598587 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 71598587 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 71598587 # number of overall hits 555system.cpu.icache.overall_hits::total 71598587 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 4691 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 4691 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses 561system.cpu.icache.overall_misses::total 4691 # number of overall misses 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 200040248 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 200040248 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 200040248 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 200040248 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 71603278 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 71603278 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 71603278 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 71603278 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 71603278 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 71603278 # number of overall (read+write) accesses | 548system.cpu.icache.tags.tag_accesses 143091069 # Number of tag accesses 549system.cpu.icache.tags.data_accesses 143091069 # Number of data accesses 550system.cpu.icache.ReadReq_hits::cpu.inst 71538503 # number of ReadReq hits 551system.cpu.icache.ReadReq_hits::total 71538503 # number of ReadReq hits 552system.cpu.icache.demand_hits::cpu.inst 71538503 # number of demand (read+write) hits 553system.cpu.icache.demand_hits::total 71538503 # number of demand (read+write) hits 554system.cpu.icache.overall_hits::cpu.inst 71538503 # number of overall hits 555system.cpu.icache.overall_hits::total 71538503 # number of overall hits 556system.cpu.icache.ReadReq_misses::cpu.inst 4688 # number of ReadReq misses 557system.cpu.icache.ReadReq_misses::total 4688 # number of ReadReq misses 558system.cpu.icache.demand_misses::cpu.inst 4688 # number of demand (read+write) misses 559system.cpu.icache.demand_misses::total 4688 # number of demand (read+write) misses 560system.cpu.icache.overall_misses::cpu.inst 4688 # number of overall misses 561system.cpu.icache.overall_misses::total 4688 # number of overall misses 562system.cpu.icache.ReadReq_miss_latency::cpu.inst 200735747 # number of ReadReq miss cycles 563system.cpu.icache.ReadReq_miss_latency::total 200735747 # number of ReadReq miss cycles 564system.cpu.icache.demand_miss_latency::cpu.inst 200735747 # number of demand (read+write) miss cycles 565system.cpu.icache.demand_miss_latency::total 200735747 # number of demand (read+write) miss cycles 566system.cpu.icache.overall_miss_latency::cpu.inst 200735747 # number of overall miss cycles 567system.cpu.icache.overall_miss_latency::total 200735747 # number of overall miss cycles 568system.cpu.icache.ReadReq_accesses::cpu.inst 71543191 # number of ReadReq accesses(hits+misses) 569system.cpu.icache.ReadReq_accesses::total 71543191 # number of ReadReq accesses(hits+misses) 570system.cpu.icache.demand_accesses::cpu.inst 71543191 # number of demand (read+write) accesses 571system.cpu.icache.demand_accesses::total 71543191 # number of demand (read+write) accesses 572system.cpu.icache.overall_accesses::cpu.inst 71543191 # number of overall (read+write) accesses 573system.cpu.icache.overall_accesses::total 71543191 # number of overall (read+write) accesses |
| 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses | 574system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 575system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 576system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 577system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 578system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 579system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses |
| 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 42643.412492 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 42643.412492 # average overall miss latency | 580system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660 # average ReadReq miss latency 581system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660 # average ReadReq miss latency 582system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency 583system.cpu.icache.demand_avg_miss_latency::total 42819.058660 # average overall miss latency 584system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency 585system.cpu.icache.overall_avg_miss_latency::total 42819.058660 # average overall miss latency |
| 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed | 586system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 592system.cpu.icache.fast_writes 0 # number of fast writes performed 593system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 4691 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 4691 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 4691 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 4691 # number of overall MSHR misses 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192077752 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 192077752 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192077752 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 192077752 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192077752 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 192077752 # number of overall MSHR miss cycles | 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4688 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 4688 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 4688 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192780753 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 192780753 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192780753 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 192780753 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192780753 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 192780753 # number of overall MSHR miss cycles |
| 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses | 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses |
| 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40946.014069 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40946.014069 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency | 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency |
| 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements | 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 620system.cpu.l2cache.tags.tagsinuse 2003.582702 # Cycle average of tags in use 621system.cpu.l2cache.tags.total_refs 2608 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 0.935773 # Average number of references to valid blocks. | 620system.cpu.l2cache.tags.tagsinuse 2002.534339 # Cycle average of tags in use 621system.cpu.l2cache.tags.total_refs 2603 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 2788 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 0.933644 # Average number of references to valid blocks. |
| 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 625system.cpu.l2cache.tags.occ_blocks::writebacks 3.029186 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 1509.739376 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814139 # Average occupied blocks per requestor | 625system.cpu.l2cache.tags.occ_blocks::writebacks 3.029198 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.688891 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 490.816250 # Average occupied blocks per requestor |
| 628system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy | 628system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy |
| 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046074 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.061144 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id | 629system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046042 # Average percentage of cache occupancy 630system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy 631system.cpu.l2cache.tags.occ_percent::total 0.061112 # Average percentage of cache occupancy 632system.cpu.l2cache.tags.occ_task_id_blocks::1024 2788 # Occupied blocks per task id |
| 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id | 633system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 634system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id |
| 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id | 635system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id |
| 636system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id | 636system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id |
| 637system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2007 # Occupied blocks per task id 638system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id 639system.cpu.l2cache.tags.tag_accesses 56021 # Number of tag accesses 640system.cpu.l2cache.tags.data_accesses 56021 # Number of data accesses 641system.cpu.l2cache.ReadReq_hits::cpu.inst 2527 # number of ReadReq hits | 637system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2006 # Occupied blocks per task id 638system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085083 # Percentage of cache occupancy per task id 639system.cpu.l2cache.tags.tag_accesses 55998 # Number of tag accesses 640system.cpu.l2cache.tags.data_accesses 55998 # Number of data accesses 641system.cpu.l2cache.ReadReq_hits::cpu.inst 2522 # number of ReadReq hits |
| 642system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits | 642system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits |
| 643system.cpu.l2cache.ReadReq_hits::total 2607 # number of ReadReq hits | 643system.cpu.l2cache.ReadReq_hits::total 2602 # number of ReadReq hits |
| 644system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 645system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 646system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 647system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits | 644system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 645system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 646system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 647system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits |
| 648system.cpu.l2cache.demand_hits::cpu.inst 2527 # number of demand (read+write) hits | 648system.cpu.l2cache.demand_hits::cpu.inst 2522 # number of demand (read+write) hits |
| 649system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits | 649system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits |
| 650system.cpu.l2cache.demand_hits::total 2615 # number of demand (read+write) hits 651system.cpu.l2cache.overall_hits::cpu.inst 2527 # number of overall hits | 650system.cpu.l2cache.demand_hits::total 2610 # number of demand (read+write) hits 651system.cpu.l2cache.overall_hits::cpu.inst 2522 # number of overall hits |
| 652system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits | 652system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits |
| 653system.cpu.l2cache.overall_hits::total 2615 # number of overall hits 654system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses | 653system.cpu.l2cache.overall_hits::total 2610 # number of overall hits 654system.cpu.l2cache.ReadReq_misses::cpu.inst 2166 # number of ReadReq misses |
| 655system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses | 655system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses |
| 656system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses | 656system.cpu.l2cache.ReadReq_misses::total 2798 # number of ReadReq misses |
| 657system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses 658system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses | 657system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses 658system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses |
| 659system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses | 659system.cpu.l2cache.demand_misses::cpu.inst 2166 # number of demand (read+write) misses |
| 660system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses | 660system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses |
| 661system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses 662system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses | 661system.cpu.l2cache.demand_misses::total 3888 # number of demand (read+write) misses 662system.cpu.l2cache.overall_misses::cpu.inst 2166 # number of overall misses |
| 663system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses | 663system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses |
| 664system.cpu.l2cache.overall_misses::total 3886 # number of overall misses 665system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160854250 # number of ReadReq miss cycles 666system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51424250 # number of ReadReq miss cycles 667system.cpu.l2cache.ReadReq_miss_latency::total 212278500 # number of ReadReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84027000 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadExReq_miss_latency::total 84027000 # number of ReadExReq miss cycles 670system.cpu.l2cache.demand_miss_latency::cpu.inst 160854250 # number of demand (read+write) miss cycles 671system.cpu.l2cache.demand_miss_latency::cpu.data 135451250 # number of demand (read+write) miss cycles 672system.cpu.l2cache.demand_miss_latency::total 296305500 # number of demand (read+write) miss cycles 673system.cpu.l2cache.overall_miss_latency::cpu.inst 160854250 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_latency::cpu.data 135451250 # number of overall miss cycles 675system.cpu.l2cache.overall_miss_latency::total 296305500 # number of overall miss cycles 676system.cpu.l2cache.ReadReq_accesses::cpu.inst 4691 # number of ReadReq accesses(hits+misses) | 664system.cpu.l2cache.overall_misses::total 3888 # number of overall misses 665system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161612750 # number of ReadReq miss cycles 666system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49681750 # number of ReadReq miss cycles 667system.cpu.l2cache.ReadReq_miss_latency::total 211294500 # number of ReadReq miss cycles 668system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83135500 # number of ReadExReq miss cycles 669system.cpu.l2cache.ReadExReq_miss_latency::total 83135500 # number of ReadExReq miss cycles 670system.cpu.l2cache.demand_miss_latency::cpu.inst 161612750 # number of demand (read+write) miss cycles 671system.cpu.l2cache.demand_miss_latency::cpu.data 132817250 # number of demand (read+write) miss cycles 672system.cpu.l2cache.demand_miss_latency::total 294430000 # number of demand (read+write) miss cycles 673system.cpu.l2cache.overall_miss_latency::cpu.inst 161612750 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_latency::cpu.data 132817250 # number of overall miss cycles 675system.cpu.l2cache.overall_miss_latency::total 294430000 # number of overall miss cycles 676system.cpu.l2cache.ReadReq_accesses::cpu.inst 4688 # number of ReadReq accesses(hits+misses) |
| 677system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) | 677system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) |
| 678system.cpu.l2cache.ReadReq_accesses::total 5403 # number of ReadReq accesses(hits+misses) | 678system.cpu.l2cache.ReadReq_accesses::total 5400 # number of ReadReq accesses(hits+misses) |
| 679system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) | 679system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 680system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 681system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 682system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) |
| 683system.cpu.l2cache.demand_accesses::cpu.inst 4691 # number of demand (read+write) accesses | 683system.cpu.l2cache.demand_accesses::cpu.inst 4688 # number of demand (read+write) accesses |
| 684system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses | 684system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses |
| 685system.cpu.l2cache.demand_accesses::total 6501 # number of demand (read+write) accesses 686system.cpu.l2cache.overall_accesses::cpu.inst 4691 # number of overall (read+write) accesses | 685system.cpu.l2cache.demand_accesses::total 6498 # number of demand (read+write) accesses 686system.cpu.l2cache.overall_accesses::cpu.inst 4688 # number of overall (read+write) accesses |
| 687system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses | 687system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses |
| 688system.cpu.l2cache.overall_accesses::total 6501 # number of overall (read+write) accesses 689system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461309 # miss rate for ReadReq accesses | 688system.cpu.l2cache.overall_accesses::total 6498 # number of overall (read+write) accesses 689system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462031 # miss rate for ReadReq accesses |
| 690system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses | 690system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses |
| 691system.cpu.l2cache.ReadReq_miss_rate::total 0.517490 # miss rate for ReadReq accesses | 691system.cpu.l2cache.ReadReq_miss_rate::total 0.518148 # miss rate for ReadReq accesses |
| 692system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses 693system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses | 692system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses 693system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses |
| 694system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461309 # miss rate for demand accesses | 694system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462031 # miss rate for demand accesses |
| 695system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses | 695system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses |
| 696system.cpu.l2cache.demand_miss_rate::total 0.597754 # miss rate for demand accesses 697system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461309 # miss rate for overall accesses | 696system.cpu.l2cache.demand_miss_rate::total 0.598338 # miss rate for demand accesses 697system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462031 # miss rate for overall accesses |
| 698system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses | 698system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses |
| 699system.cpu.l2cache.overall_miss_rate::total 0.597754 # miss rate for overall accesses 700system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74331.908503 # average ReadReq miss latency 701system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81367.484177 # average ReadReq miss latency 702system.cpu.l2cache.ReadReq_avg_miss_latency::total 75922.210300 # average ReadReq miss latency 703system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77088.990826 # average ReadExReq miss latency 704system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77088.990826 # average ReadExReq miss latency 705system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74331.908503 # average overall miss latency 706system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78659.262485 # average overall miss latency 707system.cpu.l2cache.demand_avg_miss_latency::total 76249.485332 # average overall miss latency 708system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74331.908503 # average overall miss latency 709system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78659.262485 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::total 76249.485332 # average overall miss latency | 699system.cpu.l2cache.overall_miss_rate::total 0.598338 # miss rate for overall accesses 700system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74613.457987 # average ReadReq miss latency 701system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78610.363924 # average ReadReq miss latency 702system.cpu.l2cache.ReadReq_avg_miss_latency::total 75516.261615 # average ReadReq miss latency 703system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76271.100917 # average ReadExReq miss latency 704system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76271.100917 # average ReadExReq miss latency 705system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency 706system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency 707system.cpu.l2cache.demand_avg_miss_latency::total 75727.880658 # average overall miss latency 708system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency 709system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency 710system.cpu.l2cache.overall_avg_miss_latency::total 75727.880658 # average overall miss latency |
| 711system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu.l2cache.fast_writes 0 # number of fast writes performed 718system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 711system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu.l2cache.fast_writes 0 # number of fast writes performed 718system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 719system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits | 719system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits |
| 720system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits | 720system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits |
| 721system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 722system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits | 721system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 722system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits |
| 723system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits | 723system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits |
| 724system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 725system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits | 724system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 725system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits |
| 726system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits | 726system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits |
| 727system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 728system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses | 727system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 728system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2163 # number of ReadReq MSHR misses |
| 729system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses | 729system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses |
| 730system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses | 730system.cpu.l2cache.ReadReq_mshr_misses::total 2781 # number of ReadReq MSHR misses |
| 731system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses 732system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses | 731system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses 732system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses |
| 733system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses | 733system.cpu.l2cache.demand_mshr_misses::cpu.inst 2163 # number of demand (read+write) MSHR misses |
| 734system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses | 734system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses |
| 735system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses 736system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses | 735system.cpu.l2cache.demand_mshr_misses::total 3871 # number of demand (read+write) MSHR misses 736system.cpu.l2cache.overall_mshr_misses::cpu.inst 2163 # number of overall MSHR misses |
| 737system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses | 737system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses |
| 738system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses 739system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 133664500 # number of ReadReq MSHR miss cycles 740system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42488500 # number of ReadReq MSHR miss cycles 741system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176153000 # number of ReadReq MSHR miss cycles 742system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70398000 # number of ReadExReq MSHR miss cycles 743system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70398000 # number of ReadExReq MSHR miss cycles 744system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 133664500 # number of demand (read+write) MSHR miss cycles 745system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112886500 # number of demand (read+write) MSHR miss cycles 746system.cpu.l2cache.demand_mshr_miss_latency::total 246551000 # number of demand (read+write) MSHR miss cycles 747system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 133664500 # number of overall MSHR miss cycles 748system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112886500 # number of overall MSHR miss cycles 749system.cpu.l2cache.overall_mshr_miss_latency::total 246551000 # number of overall MSHR miss cycles 750system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for ReadReq accesses | 738system.cpu.l2cache.overall_mshr_misses::total 3871 # number of overall MSHR misses 739system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134379750 # number of ReadReq MSHR miss cycles 740system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40985000 # number of ReadReq MSHR miss cycles 741system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175364750 # number of ReadReq MSHR miss cycles 742system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69507000 # number of ReadExReq MSHR miss cycles 743system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69507000 # number of ReadExReq MSHR miss cycles 744system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134379750 # number of demand (read+write) MSHR miss cycles 745system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110492000 # number of demand (read+write) MSHR miss cycles 746system.cpu.l2cache.demand_mshr_miss_latency::total 244871750 # number of demand (read+write) MSHR miss cycles 747system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134379750 # number of overall MSHR miss cycles 748system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110492000 # number of overall MSHR miss cycles 749system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles 750system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses |
| 751system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses | 751system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses |
| 752system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514529 # mshr miss rate for ReadReq accesses | 752system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses |
| 753system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 754system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses | 753system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 754system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses |
| 755system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for demand accesses | 755system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses |
| 756system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses | 756system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses |
| 757system.cpu.l2cache.demand_mshr_miss_rate::total 0.595293 # mshr miss rate for demand accesses 758system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for overall accesses | 757system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses 758system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses |
| 759system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses | 759system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses |
| 760system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses 761system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency 762system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency 763system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency 764system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency 765system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency 766system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency 767system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency 768system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency 769system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency 770system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency 771system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency | 760system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses 761system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency 762system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency 763system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency 764system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency 765system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency 766system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency 767system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency 768system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency 769system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency 770system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency 771system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency |
| 772system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 772system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 773system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution 774system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution | 773system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution 774system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution |
| 775system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 776system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 777system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution | 775system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 776system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 777system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution |
| 778system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes) | 778system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes) |
| 779system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) | 779system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) |
| 780system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes) 781system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes) | 780system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes) 781system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes) |
| 782system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) | 782system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) |
| 783system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes) | 783system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes) |
| 784system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 784system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 785system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram | 785system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram |
| 786system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 787system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 788system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 789system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 786system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 787system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 788system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 789system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 790system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram | 790system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram |
| 791system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 792system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 793system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 794system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 791system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 792system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 793system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 794system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 795system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram 796system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks) | 795system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram 796system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks) |
| 797system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 797system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 798system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks) | 798system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks) |
| 799system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 800system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) 801system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 799system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 800system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) 801system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 802system.membus.trans_dist::ReadReq 2779 # Transaction distribution 803system.membus.trans_dist::ReadResp 2779 # Transaction distribution | 802system.membus.trans_dist::ReadReq 2780 # Transaction distribution 803system.membus.trans_dist::ReadResp 2780 # Transaction distribution |
| 804system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 805system.membus.trans_dist::ReadExResp 1090 # Transaction distribution | 804system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 805system.membus.trans_dist::ReadExResp 1090 # Transaction distribution |
| 806system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) 807system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) 808system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) 809system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) | 806system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes) 807system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes) 808system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes) 809system.membus.pkt_size::total 247680 # Cumulative packet size per connected master and slave (bytes) |
| 810system.membus.snoops 0 # Total snoops (count) | 810system.membus.snoops 0 # Total snoops (count) |
| 811system.membus.snoop_fanout::samples 3869 # Request fanout histogram | 811system.membus.snoop_fanout::samples 3870 # Request fanout histogram |
| 812system.membus.snoop_fanout::mean 0 # Request fanout histogram 813system.membus.snoop_fanout::stdev 0 # Request fanout histogram 814system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 812system.membus.snoop_fanout::mean 0 # Request fanout histogram 813system.membus.snoop_fanout::stdev 0 # Request fanout histogram 814system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 815system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram | 815system.membus.snoop_fanout::0 3870 100.00% 100.00% # Request fanout histogram |
| 816system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 817system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 818system.membus.snoop_fanout::min_value 0 # Request fanout histogram 819system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 816system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 817system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 818system.membus.snoop_fanout::min_value 0 # Request fanout histogram 819system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 820system.membus.snoop_fanout::total 3869 # Request fanout histogram 821system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks) | 820system.membus.snoop_fanout::total 3870 # Request fanout histogram 821system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) |
| 822system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 822system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 823system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks) | 823system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks) |
| 824system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 825 826---------- End Simulation Statistics ---------- | 824system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 825 826---------- End Simulation Statistics ---------- |