| stats.txt (10636:9ac724889705) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.131746 # Number of seconds simulated 4sim_ticks 131745950000 # Number of ticks simulated 5final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.131756 # Number of seconds simulated 4sim_ticks 131756455500 # Number of ticks simulated 5final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 165378 # Simulator instruction rate (inst/s) 8host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 126440065 # Simulator tick rate (ticks/s) 10host_mem_usage 304748 # Number of bytes of host memory used 11host_seconds 1041.96 # Real time elapsed on the host | 7host_inst_rate 249754 # Simulator instruction rate (inst/s) 8host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 190965456 # Simulator tick rate (ticks/s) 10host_mem_usage 316672 # Number of bytes of host memory used 11host_seconds 689.95 # Real time elapsed on the host |
| 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 247488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 247616 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory | 22system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3867 # Number of read requests accepted | 23system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 3869 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 305 # Per bank write bursts 45system.physmem.perBankRdBursts::1 217 # Per bank write bursts 46system.physmem.perBankRdBursts::2 135 # Per bank write bursts 47system.physmem.perBankRdBursts::3 313 # Per bank write bursts | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 305 # Per bank write bursts 45system.physmem.perBankRdBursts::1 217 # Per bank write bursts 46system.physmem.perBankRdBursts::2 135 # Per bank write bursts 47system.physmem.perBankRdBursts::3 313 # Per bank write bursts |
| 48system.physmem.perBankRdBursts::4 308 # Per bank write bursts | 48system.physmem.perBankRdBursts::4 307 # Per bank write bursts |
| 49system.physmem.perBankRdBursts::5 305 # Per bank write bursts 50system.physmem.perBankRdBursts::6 273 # Per bank write bursts 51system.physmem.perBankRdBursts::7 222 # Per bank write bursts 52system.physmem.perBankRdBursts::8 249 # Per bank write bursts 53system.physmem.perBankRdBursts::9 218 # Per bank write bursts 54system.physmem.perBankRdBursts::10 295 # Per bank write bursts | 49system.physmem.perBankRdBursts::5 305 # Per bank write bursts 50system.physmem.perBankRdBursts::6 273 # Per bank write bursts 51system.physmem.perBankRdBursts::7 222 # Per bank write bursts 52system.physmem.perBankRdBursts::8 249 # Per bank write bursts 53system.physmem.perBankRdBursts::9 218 # Per bank write bursts 54system.physmem.perBankRdBursts::10 295 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::11 199 # Per bank write bursts | 55system.physmem.perBankRdBursts::11 201 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::12 183 # Per bank write bursts 57system.physmem.perBankRdBursts::13 218 # Per bank write bursts 58system.physmem.perBankRdBursts::14 224 # Per bank write bursts | 56system.physmem.perBankRdBursts::12 183 # Per bank write bursts 57system.physmem.perBankRdBursts::13 218 # Per bank write bursts 58system.physmem.perBankRdBursts::14 224 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::15 203 # Per bank write bursts | 59system.physmem.perBankRdBursts::15 204 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 131745861500 # Total gap between requests | 78system.physmem.totGap 131756361000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 3867 # Read request sizes (log2) | 85system.physmem.readPktSize::6 3869 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation 203system.physmem.totQLat 28130750 # Total ticks spent queuing 204system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation 203system.physmem.totQLat 26801000 # Total ticks spent queuing 204system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 209system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.01 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 2950 # Number of row buffer hits during reads | 219system.physmem.readRowHits 2968 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 34069268.55 # Average gap between requests 224system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 34054370.90 # Average gap between requests 224system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.807422 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states | 229system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) 233system.physmem_0.averagePower 668.773044 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states |
| 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.815773 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states | 243system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) 247system.physmem_1.averagePower 668.806861 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states 249system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 49935043 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits | 253system.cpu.branchPred.lookups 49934480 # Number of BP lookups 254system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. | 259system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. |
| 261system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls | 261system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst --- 103 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 400 # Number of system calls |
| 380system.cpu.numCycles 263491900 # number of cpu cycles simulated | 380system.cpu.numCycles 263512911 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317809 # Number of instructions committed 384system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 172317809 # Number of instructions committed 384system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed |
| 385system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit | 385system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit |
| 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 387system.cpu.cpi 1.529104 # CPI: cycles per instruction 388system.cpu.ipc 0.653978 # IPC: instructions per cycle 389system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 1.529226 # CPI: cycles per instruction 388system.cpu.ipc 0.653925 # IPC: instructions per cycle 389system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 42 # number of replacements | 391system.cpu.dcache.tags.replacements 42 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. | 392system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. |
| 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. | 394system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. |
| 395system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. | 395system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. |
| 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy | 397system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy |
| 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id | 400system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id |
| 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id | 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id |
| 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id | 403system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id 406system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id |
| 407system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits 411system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits | 407system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses 408system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses 409system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits 410system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits 411system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits 412system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits |
| 413system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 414system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 415system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 416system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 413system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 414system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 415system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 416system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 417system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits 418system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits 419system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits 420system.cpu.dcache.overall_hits::total 40718173 # number of overall hits 421system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses 422system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses 423system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses 424system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses | 417system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits 418system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits 419system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits 420system.cpu.dcache.overall_hits::total 40720863 # number of overall hits 421system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses 422system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses 423system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses 424system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses |
| 425system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses 426system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses 427system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses 428system.cpu.dcache.overall_misses::total 2436 # number of overall misses | 425system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses 426system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses 427system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses 428system.cpu.dcache.overall_misses::total 2436 # number of overall misses |
| 429system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles 430system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles 431system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles 432system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles 433system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles 434system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles 435system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles 436system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles 437system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) 438system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) | 429system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles 430system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles 431system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles 432system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles 433system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles 434system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles 435system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles 436system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles 437system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) 438system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) |
| 439system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 440system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 441system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 442system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 443system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 444system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 439system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 440system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 441system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 442system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 443system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 444system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 445system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses 446system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses 447system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses 448system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses | 445system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses 446system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses 447system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses 448system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses |
| 449system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses 450system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses 451system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 452system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 453system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 454system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 455system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 456system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses | 449system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses 450system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses 451system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 452system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 453system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 454system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 455system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 456system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses |
| 457system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency 458system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency 459system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency 460system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency 461system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency 462system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency 463system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency 464system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency | 457system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency 458system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency 459system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency 460system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency 461system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency 462system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency 463system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency 464system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency |
| 465system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 466system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 467system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 468system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 469system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 470system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 471system.cpu.dcache.fast_writes 0 # number of fast writes performed 472system.cpu.dcache.cache_copies 0 # number of cache copies performed 473system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 474system.cpu.dcache.writebacks::total 16 # number of writebacks | 465system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 466system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 467system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 468system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 469system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 470system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 471system.cpu.dcache.fast_writes 0 # number of fast writes performed 472system.cpu.dcache.cache_copies 0 # number of cache copies performed 473system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 474system.cpu.dcache.writebacks::total 16 # number of writebacks |
| 475system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits 476system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits 477system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits 478system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits | 475system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 476system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 477system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 478system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits |
| 479system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits 480system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits 481system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits 482system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits 483system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq MSHR misses 484system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses 485system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 486system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 487system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses 488system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses 489system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 490system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses | 479system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits 480system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits 481system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits 482system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits 483system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq MSHR misses 484system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses 485system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses 486system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 487system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses 488system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses 489system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses 490system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses |
| 491system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles 492system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles 493system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles 494system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles 495system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles 496system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles 497system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles 498system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles | 491system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles 492system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles 493system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles 494system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles 495system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles 496system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles 497system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles 498system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles |
| 499system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 500system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 501system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 502system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 503system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 504system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 505system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 506system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses | 499system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 500system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 501system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 502system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 503system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 504system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 505system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 506system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses |
| 507system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency 508system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency 509system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency 510system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency 511system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency 512system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency 513system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency 514system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency | 507system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency 508system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency 509system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency 510system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency 511system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency 512system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency 513system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency 514system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency |
| 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 516system.cpu.icache.tags.replacements 2909 # number of replacements 517system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use 518system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. 519system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. 520system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. | 516system.cpu.icache.tags.replacements 2891 # number of replacements 517system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use 518system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. 519system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. 520system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. |
| 521system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 521system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 522system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor 523system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy 524system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy 525system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id | 522system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor 523system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy 524system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy 525system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id |
| 526system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 527system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id | 526system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 527system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id |
| 528system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id 529system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id 530system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id 531system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id 532system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses 533system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses 534system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits 535system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits 536system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits 537system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits 538system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits 539system.cpu.icache.overall_hits::total 71614329 # number of overall hits 540system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses 541system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses 542system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses 543system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses 544system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses 545system.cpu.icache.overall_misses::total 4706 # number of overall misses 546system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles 547system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles 548system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles 549system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles 550system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles 551system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles 552system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) 553system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) 554system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses 555system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses 556system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses 557system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses 558system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 559system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 560system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 561system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 562system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 563system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses 564system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency 565system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency 566system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency 567system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency 568system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency 569system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency | 528system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id 529system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id 530system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id 531system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id 532system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses 533system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses 534system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits 535system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits 536system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits 537system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits 538system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits 539system.cpu.icache.overall_hits::total 71597357 # number of overall hits 540system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses 541system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses 542system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses 543system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses 544system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses 545system.cpu.icache.overall_misses::total 4689 # number of overall misses 546system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles 547system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles 548system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles 549system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles 550system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles 551system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles 552system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) 553system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) 554system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses 555system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses 556system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses 557system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses 558system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses 559system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses 560system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses 561system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses 562system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses 563system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses 564system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency 565system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency 566system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency 567system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency 568system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency 569system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency |
| 570system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 571system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 572system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 573system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 574system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 575system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 576system.cpu.icache.fast_writes 0 # number of fast writes performed 577system.cpu.icache.cache_copies 0 # number of cache copies performed | 570system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 571system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 572system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 573system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 574system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 575system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 576system.cpu.icache.fast_writes 0 # number of fast writes performed 577system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 578system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses 579system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses 580system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses 581system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses 582system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses 583system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses 584system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles 585system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles 586system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles 587system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles 588system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles 589system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles 590system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 591system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 592system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 593system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 594system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 595system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 596system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency 597system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency 598system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency 599system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency 600system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency 601system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency | 578system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses 579system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses 580system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses 581system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses 582system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses 583system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses 584system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles 585system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles 586system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles 587system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles 588system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles 589system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles 590system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses 591system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses 592system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses 593system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses 594system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses 595system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses 596system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency 597system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency 598system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency 599system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency 600system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency 601system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency |
| 602system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.cpu.l2cache.tags.replacements 0 # number of replacements | 602system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 604system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use 605system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. 606system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. 607system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. | 604system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use 605system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. 606system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. 607system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. |
| 608system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 608system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 609system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor 610system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor 611system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor | 609system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor 610system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor 611system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor |
| 612system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy | 612system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy |
| 613system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy 614system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy | 613system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy 614system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy |
| 615system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy | 615system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy |
| 616system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id 617system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 618system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 619system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id 620system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id | 616system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id 617system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 618system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 619system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id 620system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id |
| 621system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id | 621system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id |
| 622system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id 623system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses 624system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses 625system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits | 622system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id 623system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses 624system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses 625system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits |
| 626system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits | 626system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits |
| 627system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits | 627system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits |
| 628system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 629system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 630system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 631system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits | 628system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 629system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 630system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 631system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits |
| 632system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits | 632system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits |
| 633system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits | 633system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits |
| 634system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits 635system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits | 634system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits 635system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits |
| 636system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits | 636system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits |
| 637system.cpu.l2cache.overall_hits::total 2631 # number of overall hits 638system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses | 637system.cpu.l2cache.overall_hits::total 2613 # number of overall hits 638system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses |
| 639system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses | 639system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses |
| 640system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses | 640system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses |
| 641system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses 642system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses | 641system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses 642system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses |
| 643system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses | 643system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses |
| 644system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses | 644system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses |
| 645system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses 646system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses | 645system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses 646system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses |
| 647system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses | 647system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses |
| 648system.cpu.l2cache.overall_misses::total 3885 # number of overall misses 649system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles 650system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles 651system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles 652system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles 653system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles 654system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles 655system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles 656system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles 657system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles 658system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles 659system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles 660system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses) | 648system.cpu.l2cache.overall_misses::total 3886 # number of overall misses 649system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles 650system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles 651system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles 652system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles 653system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles 654system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles 655system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles 656system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles 657system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles 658system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles 659system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles 660system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses) |
| 661system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) | 661system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) |
| 662system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) | 662system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) |
| 663system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 664system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 665system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 666system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) | 663system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 664system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 665system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) 666system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) |
| 667system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses | 667system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses |
| 668system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses | 668system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses |
| 669system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses 670system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses | 669system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses 670system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses |
| 671system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses | 671system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses |
| 672system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses 673system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses | 672system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses 673system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses |
| 674system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses | 674system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses |
| 675system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses | 675system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses |
| 676system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses | 676system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses 677system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses |
| 678system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses | 678system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses |
| 679system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses | 679system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses |
| 680system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses 681system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses | 680system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses 681system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses |
| 682system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses | 682system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses |
| 683system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses 684system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency 685system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency 686system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency 687system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency 688system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency 689system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency 690system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency 691system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency 692system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency 693system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency 694system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency | 683system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses 684system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency 685system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency 686system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency 687system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency 688system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency 689system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency 690system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency 691system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency 692system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency 693system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency 694system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency |
| 695system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 696system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 697system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 698system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 699system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 700system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 701system.cpu.l2cache.fast_writes 0 # number of fast writes performed 702system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 695system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 696system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 697system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 698system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 699system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 700system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 701system.cpu.l2cache.fast_writes 0 # number of fast writes performed 702system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 703system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits | 703system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits |
| 704system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits | 704system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits |
| 705system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 706system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits | 705system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits 706system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits |
| 707system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits | 707system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits |
| 708system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 709system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits | 708system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 709system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits |
| 710system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits | 710system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits |
| 711system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 712system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses | 711system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 712system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses |
| 713system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses | 713system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses |
| 714system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses | 714system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses |
| 715system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses 716system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses | 715system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses 716system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses |
| 717system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses | 717system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses |
| 718system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses | 718system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses |
| 719system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses 720system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses | 719system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses 720system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses |
| 721system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses | 721system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses |
| 722system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses 723system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles 724system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles 725system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles 726system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles 727system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles 728system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles 729system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles 732system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles 734system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses | 722system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses 723system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles 724system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles 725system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles 726system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles 727system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles 728system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles 729system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles 732system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles 733system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles 734system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses |
| 735system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses | 735system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses |
| 736system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses | 736system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses |
| 737system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 738system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses | 737system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses 738system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses |
| 739system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses | 739system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses |
| 740system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses | 740system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses |
| 741system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses 742system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses | 741system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses 742system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses |
| 743system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses | 743system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses |
| 744system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses 745system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency 746system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency 749system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency 750system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency 751system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency 753system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency 754system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency | 744system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses 745system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency 746system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency 749system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency 750system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency 751system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency 753system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency 754system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency 755system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency |
| 756system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 756system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 757system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution 758system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution | 757system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution 758system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution |
| 759system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 760system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 761system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution | 759system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 760system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 761system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution |
| 762system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) | 762system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) |
| 763system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) | 763system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) |
| 764system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) 765system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) | 764system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) 765system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) |
| 766system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) | 766system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) |
| 767system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) | 767system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) |
| 768system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 768system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 769system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 769system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 771system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 772system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 775system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 771system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 772system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 775system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 776system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 777system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 778system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram 779system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 776system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram 777system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 780system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 778system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 781system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 782system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 783system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram 784system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) | 779system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 780system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 781system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram 782system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) |
| 785system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 783system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 786system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) | 784system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) |
| 787system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 785system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 788system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) | 786system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) |
| 789system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 787system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 790system.membus.trans_dist::ReadReq 2777 # Transaction distribution 791system.membus.trans_dist::ReadResp 2777 # Transaction distribution | 788system.membus.trans_dist::ReadReq 2779 # Transaction distribution 789system.membus.trans_dist::ReadResp 2779 # Transaction distribution |
| 792system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 793system.membus.trans_dist::ReadExResp 1090 # Transaction distribution | 790system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 791system.membus.trans_dist::ReadExResp 1090 # Transaction distribution |
| 794system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) 795system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) 796system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) 797system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) | 792system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) 793system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) 794system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) 795system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) |
| 798system.membus.snoops 0 # Total snoops (count) | 796system.membus.snoops 0 # Total snoops (count) |
| 799system.membus.snoop_fanout::samples 3867 # Request fanout histogram | 797system.membus.snoop_fanout::samples 3869 # Request fanout histogram |
| 800system.membus.snoop_fanout::mean 0 # Request fanout histogram 801system.membus.snoop_fanout::stdev 0 # Request fanout histogram 802system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 798system.membus.snoop_fanout::mean 0 # Request fanout histogram 799system.membus.snoop_fanout::stdev 0 # Request fanout histogram 800system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 803system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram | 801system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram |
| 804system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 805system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 806system.membus.snoop_fanout::min_value 0 # Request fanout histogram 807system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 802system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 803system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 804system.membus.snoop_fanout::min_value 0 # Request fanout histogram 805system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 808system.membus.snoop_fanout::total 3867 # Request fanout histogram 809system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) | 806system.membus.snoop_fanout::total 3869 # Request fanout histogram 807system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) |
| 810system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 808system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 811system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) | 809system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) |
| 812system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 813 814---------- End Simulation Statistics ---------- | 810system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 811 812---------- End Simulation Statistics ---------- |