| stats.txt (10433:821cbe4a183b) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.131652 # Number of seconds simulated 4sim_ticks 131652469500 # Number of ticks simulated 5final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.131746 # Number of seconds simulated 4sim_ticks 131745950000 # Number of ticks simulated 5final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 162179 # Simulator instruction rate (inst/s) 8host_op_rate 170963 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 123906567 # Simulator tick rate (ticks/s) 10host_mem_usage 259776 # Number of bytes of host memory used 11host_seconds 1062.51 # Real time elapsed on the host | 7host_inst_rate 190259 # Simulator instruction rate (inst/s) 8host_op_rate 200564 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 145463120 # Simulator tick rate (ticks/s) 10host_mem_usage 256996 # Number of bytes of host memory used 11host_seconds 905.70 # Real time elapsed on the host |
| 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory 17system.physmem.bytes_read::total 247616 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 3869 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1880831 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 1880831 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 1050523 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 1050523 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 1880831 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 1880831 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.readReqs 3869 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory 17system.physmem.bytes_read::total 247488 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 3867 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1878525 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.readReqs 3867 # Number of read requests accepted |
| 29system.physmem.writeReqs 0 # Number of write requests accepted | 29system.physmem.writeReqs 0 # Number of write requests accepted |
| 30system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue | 30system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue |
| 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 32system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM | 32system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM |
| 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 35system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side | 35system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side |
| 36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 40system.physmem.perBankRdBursts::0 305 # Per bank write bursts 41system.physmem.perBankRdBursts::1 217 # Per bank write bursts 42system.physmem.perBankRdBursts::2 135 # Per bank write bursts 43system.physmem.perBankRdBursts::3 313 # Per bank write bursts 44system.physmem.perBankRdBursts::4 308 # Per bank write bursts | 36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 40system.physmem.perBankRdBursts::0 305 # Per bank write bursts 41system.physmem.perBankRdBursts::1 217 # Per bank write bursts 42system.physmem.perBankRdBursts::2 135 # Per bank write bursts 43system.physmem.perBankRdBursts::3 313 # Per bank write bursts 44system.physmem.perBankRdBursts::4 308 # Per bank write bursts |
| 45system.physmem.perBankRdBursts::5 306 # Per bank write bursts | 45system.physmem.perBankRdBursts::5 305 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::6 273 # Per bank write bursts 47system.physmem.perBankRdBursts::7 222 # Per bank write bursts 48system.physmem.perBankRdBursts::8 249 # Per bank write bursts 49system.physmem.perBankRdBursts::9 218 # Per bank write bursts 50system.physmem.perBankRdBursts::10 295 # Per bank write bursts | 46system.physmem.perBankRdBursts::6 273 # Per bank write bursts 47system.physmem.perBankRdBursts::7 222 # Per bank write bursts 48system.physmem.perBankRdBursts::8 249 # Per bank write bursts 49system.physmem.perBankRdBursts::9 218 # Per bank write bursts 50system.physmem.perBankRdBursts::10 295 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::11 201 # Per bank write bursts 52system.physmem.perBankRdBursts::12 182 # Per bank write bursts | 51system.physmem.perBankRdBursts::11 199 # Per bank write bursts 52system.physmem.perBankRdBursts::12 183 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::13 218 # Per bank write bursts 54system.physmem.perBankRdBursts::14 224 # Per bank write bursts 55system.physmem.perBankRdBursts::15 203 # Per bank write bursts 56system.physmem.perBankWrBursts::0 0 # Per bank write bursts 57system.physmem.perBankWrBursts::1 0 # Per bank write bursts 58system.physmem.perBankWrBursts::2 0 # Per bank write bursts 59system.physmem.perBankWrBursts::3 0 # Per bank write bursts 60system.physmem.perBankWrBursts::4 0 # Per bank write bursts --- 5 unchanged lines hidden (view full) --- 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 53system.physmem.perBankRdBursts::13 218 # Per bank write bursts 54system.physmem.perBankRdBursts::14 224 # Per bank write bursts 55system.physmem.perBankRdBursts::15 203 # Per bank write bursts 56system.physmem.perBankWrBursts::0 0 # Per bank write bursts 57system.physmem.perBankWrBursts::1 0 # Per bank write bursts 58system.physmem.perBankWrBursts::2 0 # Per bank write bursts 59system.physmem.perBankWrBursts::3 0 # Per bank write bursts 60system.physmem.perBankWrBursts::4 0 # Per bank write bursts --- 5 unchanged lines hidden (view full) --- 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 74system.physmem.totGap 131652381500 # Total gap between requests | 74system.physmem.totGap 131745861500 # Total gap between requests |
| 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) | 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 81system.physmem.readPktSize::6 3869 # Read request sizes (log2) | 81system.physmem.readPktSize::6 3867 # Read request sizes (log2) |
| 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) 89system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see | 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) 89system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see |
| 90system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see | 90system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see |
| 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 185system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation 199system.physmem.totQLat 27698500 # Total ticks spent queuing 200system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM 201system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers 202system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst | 185system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation 199system.physmem.totQLat 28129500 # Total ticks spent queuing 200system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM 201system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers 202system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst | 204system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst |
| 205system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.01 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 205system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.01 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 215system.physmem.readRowHits 2960 # Number of row buffer hits during reads | 215system.physmem.readRowHits 2950 # Number of row buffer hits during reads |
| 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 217system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads | 217system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads |
| 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 219system.physmem.avgGap 34027495.86 # Average gap between requests 220system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states 222system.physmem.memoryStateTime::REF 4396080000 # Time in different power states | 219system.physmem.avgGap 34069268.55 # Average gap between requests 220system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states 222system.physmem.memoryStateTime::REF 4399200000 # Time in different power states |
| 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 224system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states | 224system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states |
| 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 226system.physmem.actEnergy::0 3039120 # Energy for activate commands per rank (pJ) 227system.physmem.actEnergy::1 3780000 # Energy for activate commands per rank (pJ) 228system.physmem.preEnergy::0 1658250 # Energy for precharge commands per rank (pJ) 229system.physmem.preEnergy::1 2062500 # Energy for precharge commands per rank (pJ) 230system.physmem.readEnergy::0 16185000 # Energy for read commands per rank (pJ) 231system.physmem.readEnergy::1 13774800 # Energy for read commands per rank (pJ) | 226system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ) 227system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) 228system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ) 229system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) 230system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ) 231system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ) |
| 232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) | 232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) |
| 234system.physmem.refreshEnergy::0 8598732480 # Energy for refresh commands per rank (pJ) 235system.physmem.refreshEnergy::1 8598732480 # Energy for refresh commands per rank (pJ) 236system.physmem.actBackEnergy::0 3574139400 # Energy for active background per rank (pJ) 237system.physmem.actBackEnergy::1 3578406705 # Energy for active background per rank (pJ) 238system.physmem.preBackEnergy::0 75854895000 # Energy for precharge background per rank (pJ) 239system.physmem.preBackEnergy::1 75851151750 # Energy for precharge background per rank (pJ) 240system.physmem.totalEnergy::0 88048649250 # Total energy per rank (pJ) 241system.physmem.totalEnergy::1 88047908235 # Total energy per rank (pJ) 242system.physmem.averagePower::0 668.807689 # Core power per rank (mW) 243system.physmem.averagePower::1 668.802060 # Core power per rank (mW) 244system.membus.trans_dist::ReadReq 2779 # Transaction distribution 245system.membus.trans_dist::ReadResp 2779 # Transaction distribution 246system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 247system.membus.trans_dist::ReadExResp 1090 # Transaction distribution 248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) 249system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) 250system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) 251system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) 252system.membus.snoops 0 # Total snoops (count) 253system.membus.snoop_fanout::samples 3869 # Request fanout histogram 254system.membus.snoop_fanout::mean 0 # Request fanout histogram 255system.membus.snoop_fanout::stdev 0 # Request fanout histogram 256system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 257system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram 258system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 259system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 260system.membus.snoop_fanout::min_value 0 # Request fanout histogram 261system.membus.snoop_fanout::max_value 0 # Request fanout histogram 262system.membus.snoop_fanout::total 3869 # Request fanout histogram 263system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) 264system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 265system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks) 266system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 267system.cpu_clk_domain.clock 500 # Clock period in ticks 268system.cpu.branchPred.lookups 49915423 # Number of BP lookups 269system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted 270system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect 271system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups 272system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits | 234system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ) 235system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ) 236system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ) 237system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ) 238system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ) 239system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ) 240system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ) 241system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ) 242system.physmem.averagePower::0 668.807404 # Core power per rank (mW) 243system.physmem.averagePower::1 668.815774 # Core power per rank (mW) 244system.cpu.branchPred.lookups 49935043 # Number of BP lookups 245system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted 246system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect 247system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits |
| 273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 274system.cpu.branchPred.BTBHitPct 95.404488 # BTB Hit Percentage 275system.cpu.branchPred.usedRAS 1905800 # Number of times the RAS was used to get a target. | 250system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage 251system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. |
| 276system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. | 252system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. |
| 253system.cpu_clk_domain.clock 500 # Clock period in ticks |
|
| 277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_accesses 0 # DTB write accesses 357system.cpu.itb.inst_accesses 0 # ITB inst accesses 358system.cpu.itb.hits 0 # DTB hits 359system.cpu.itb.misses 0 # DTB misses 360system.cpu.itb.accesses 0 # DTB accesses 361system.cpu.workload.num_syscalls 400 # Number of system calls | 254system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 255system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 256system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 257system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 258system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 259system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 331system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 332system.cpu.itb.read_accesses 0 # DTB read accesses 333system.cpu.itb.write_accesses 0 # DTB write accesses 334system.cpu.itb.inst_accesses 0 # ITB inst accesses 335system.cpu.itb.hits 0 # DTB hits 336system.cpu.itb.misses 0 # DTB misses 337system.cpu.itb.accesses 0 # DTB accesses 338system.cpu.workload.num_syscalls 400 # Number of system calls |
| 362system.cpu.numCycles 263304939 # number of cpu cycles simulated | 339system.cpu.numCycles 263491900 # number of cpu cycles simulated |
| 363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 365system.cpu.committedInsts 172317809 # Number of instructions committed 366system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed | 340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 342system.cpu.committedInsts 172317809 # Number of instructions committed 343system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed |
| 367system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit | 344system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit |
| 368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 345system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 369system.cpu.cpi 1.528019 # CPI: cycles per instruction 370system.cpu.ipc 0.654442 # IPC: instructions per cycle 371system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked 372system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped 373system.cpu.icache.tags.replacements 2881 # number of replacements 374system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use 375system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. 376system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. 377system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. 378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 379system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor 380system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy 381system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy 382system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id 383system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 384system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 385system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id 386system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id 387system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id 388system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id 389system.cpu.icache.tags.tag_accesses 143033782 # Number of tag accesses 390system.cpu.icache.tags.data_accesses 143033782 # Number of data accesses 391system.cpu.icache.ReadReq_hits::cpu.inst 71509873 # number of ReadReq hits 392system.cpu.icache.ReadReq_hits::total 71509873 # number of ReadReq hits 393system.cpu.icache.demand_hits::cpu.inst 71509873 # number of demand (read+write) hits 394system.cpu.icache.demand_hits::total 71509873 # number of demand (read+write) hits 395system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits 396system.cpu.icache.overall_hits::total 71509873 # number of overall hits 397system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses 398system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses 399system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses 400system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses 401system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses 402system.cpu.icache.overall_misses::total 4679 # number of overall misses 403system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles 404system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles 405system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles 406system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles 407system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles 408system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles 409system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) 410system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) 411system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses 412system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses 413system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses 414system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses 415system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses 416system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses 417system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses 418system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses 419system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses 420system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses 421system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency 422system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency 423system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency 424system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency 425system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency 426system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency 427system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 428system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 429system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 430system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 431system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 432system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 433system.cpu.icache.fast_writes 0 # number of fast writes performed 434system.cpu.icache.cache_copies 0 # number of cache copies performed 435system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses 436system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses 437system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses 438system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses 439system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses 440system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses 441system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles 442system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles 443system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles 444system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles 445system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles 446system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles 447system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses 448system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses 449system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses 450system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses 451system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses 452system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses 453system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency 454system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency 455system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency 456system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency 457system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency 458system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency 459system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 460system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 465system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) 471system.cpu.toL2Bus.snoops 0 # Total snoops (count) 472system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 476system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram 487system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) 488system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 489system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) 490system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 491system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) 492system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 493system.cpu.l2cache.tags.replacements 0 # number of replacements 494system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use 495system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. 496system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. 497system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. 498system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 499system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor 500system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor 501system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 502system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy 503system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy 504system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id 505system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 506system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 507system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id 508system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id 509system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id 510system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id 511system.cpu.l2cache.tags.tag_accesses 55917 # Number of tag accesses 512system.cpu.l2cache.tags.data_accesses 55917 # Number of data accesses 513system.cpu.l2cache.ReadReq_hits::cpu.inst 2591 # number of ReadReq hits 514system.cpu.l2cache.ReadReq_hits::total 2591 # number of ReadReq hits 515system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 516system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 517system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits 518system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 519system.cpu.l2cache.demand_hits::cpu.inst 2599 # number of demand (read+write) hits 520system.cpu.l2cache.demand_hits::total 2599 # number of demand (read+write) hits 521system.cpu.l2cache.overall_hits::cpu.inst 2599 # number of overall hits 522system.cpu.l2cache.overall_hits::total 2599 # number of overall hits 523system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses 524system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses 525system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses 526system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses 527system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses 528system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses 529system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses 530system.cpu.l2cache.overall_misses::total 3889 # number of overall misses 531system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles 532system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles 533system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles 534system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles 535system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles 536system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles 537system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles 538system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles 539system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) 540system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) 541system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 542system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 543system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) 544system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 545system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses 546system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses 547system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses 548system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses 549system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses 550system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses 551system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses 552system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses 553system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses 554system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses 555system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses 556system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses 557system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency 558system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency 559system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency 560system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency 561system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency 562system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency 563system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency 564system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency 565system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 566system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 567system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 568system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 569system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 570system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 571system.cpu.l2cache.fast_writes 0 # number of fast writes performed 572system.cpu.l2cache.cache_copies 0 # number of cache copies performed 573system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits 574system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits 575system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits 576system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits 577system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits 578system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits 579system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses 580system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses 581system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses 582system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses 583system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses 584system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses 585system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses 586system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses 587system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles 588system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles 589system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles 590system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles 591system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles 592system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles 593system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles 594system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles 595system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses 596system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses 597system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses 598system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 599system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses 600system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses 601system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses 602system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses 603system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency 604system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency 605system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency 606system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency 607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency 608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency 609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency 610system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency 611system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 346system.cpu.cpi 1.529104 # CPI: cycles per instruction 347system.cpu.ipc 0.653978 # IPC: instructions per cycle 348system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked 349system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped |
| 612system.cpu.dcache.tags.replacements 42 # number of replacements | 350system.cpu.dcache.tags.replacements 42 # number of replacements |
| 613system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use 614system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. 615system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. 616system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. | 351system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. |
| 617system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 618system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor 619system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy 620system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy 621system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id | 356system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy 359system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id |
| 622system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 623system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id | 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id |
| 624system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 625system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id 626system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id 627system.cpu.dcache.tags.occ_task_id_percent::1024 0.431396 # Percentage of cache occupancy per task id 628system.cpu.dcache.tags.tag_accesses 81497573 # Number of tag accesses 629system.cpu.dcache.tags.data_accesses 81497573 # Number of data accesses 630system.cpu.dcache.ReadReq_hits::cpu.inst 28338014 # number of ReadReq hits 631system.cpu.dcache.ReadReq_hits::total 28338014 # number of ReadReq hits | 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 363system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 364system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id 365system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id 366system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses 367system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses 368system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits 369system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits |
| 632system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits 633system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits 634system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits 635system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 636system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits 637system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits | 370system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits 371system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits 372system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits 373system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 374system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits 375system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| 638system.cpu.dcache.demand_hits::cpu.inst 40700657 # number of demand (read+write) hits 639system.cpu.dcache.demand_hits::total 40700657 # number of demand (read+write) hits 640system.cpu.dcache.overall_hits::cpu.inst 40700657 # number of overall hits 641system.cpu.dcache.overall_hits::total 40700657 # number of overall hits 642system.cpu.dcache.ReadReq_misses::cpu.inst 767 # number of ReadReq misses 643system.cpu.dcache.ReadReq_misses::total 767 # number of ReadReq misses | 376system.cpu.dcache.demand_hits::cpu.inst 40718173 # number of demand (read+write) hits 377system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits 378system.cpu.dcache.overall_hits::cpu.inst 40718173 # number of overall hits 379system.cpu.dcache.overall_hits::total 40718173 # number of overall hits 380system.cpu.dcache.ReadReq_misses::cpu.inst 792 # number of ReadReq misses 381system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses |
| 644system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses 645system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses | 382system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses 383system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses |
| 646system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses 647system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses 648system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses 649system.cpu.dcache.overall_misses::total 2411 # number of overall misses 650system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles 651system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles 652system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles 653system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles 654system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles 655system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles 656system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles 657system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles 658system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) 659system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) | 384system.cpu.dcache.demand_misses::cpu.inst 2436 # number of demand (read+write) misses 385system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses 386system.cpu.dcache.overall_misses::cpu.inst 2436 # number of overall misses 387system.cpu.dcache.overall_misses::total 2436 # number of overall misses 388system.cpu.dcache.ReadReq_miss_latency::cpu.inst 54011984 # number of ReadReq miss cycles 389system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles 390system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115580250 # number of WriteReq miss cycles 391system.cpu.dcache.WriteReq_miss_latency::total 115580250 # number of WriteReq miss cycles 392system.cpu.dcache.demand_miss_latency::cpu.inst 169592234 # number of demand (read+write) miss cycles 393system.cpu.dcache.demand_miss_latency::total 169592234 # number of demand (read+write) miss cycles 394system.cpu.dcache.overall_miss_latency::cpu.inst 169592234 # number of overall miss cycles 395system.cpu.dcache.overall_miss_latency::total 169592234 # number of overall miss cycles 396system.cpu.dcache.ReadReq_accesses::cpu.inst 28356322 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) |
| 660system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) 661system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 662system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) 663system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 664system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) 665system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) | 398system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) 401system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 402system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) 403system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| 666system.cpu.dcache.demand_accesses::cpu.inst 40703068 # number of demand (read+write) accesses 667system.cpu.dcache.demand_accesses::total 40703068 # number of demand (read+write) accesses 668system.cpu.dcache.overall_accesses::cpu.inst 40703068 # number of overall (read+write) accesses 669system.cpu.dcache.overall_accesses::total 40703068 # number of overall (read+write) accesses 670system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses 671system.cpu.dcache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses | 404system.cpu.dcache.demand_accesses::cpu.inst 40720609 # number of demand (read+write) accesses 405system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses 406system.cpu.dcache.overall_accesses::cpu.inst 40720609 # number of overall (read+write) accesses 407system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses 408system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses 409system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses |
| 672system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses 673system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses | 410system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses 411system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses |
| 674system.cpu.dcache.demand_miss_rate::cpu.inst 0.000059 # miss rate for demand accesses 675system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses 676system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 # miss rate for overall accesses 677system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses 678system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency 679system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency 680system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency 681system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency 682system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency 683system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency 684system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency 685system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency | 412system.cpu.dcache.demand_miss_rate::cpu.inst 0.000060 # miss rate for demand accesses 413system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 414system.cpu.dcache.overall_miss_rate::cpu.inst 0.000060 # miss rate for overall accesses 415system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses 416system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495 # average ReadReq miss latency 417system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency 418system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321 # average WriteReq miss latency 419system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321 # average WriteReq miss latency 420system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency 421system.cpu.dcache.demand_avg_miss_latency::total 69619.143678 # average overall miss latency 422system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency::total 69619.143678 # average overall miss latency |
| 686system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 687system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 688system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 689system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 690system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 691system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 692system.cpu.dcache.fast_writes 0 # number of fast writes performed 693system.cpu.dcache.cache_copies 0 # number of cache copies performed 694system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 695system.cpu.dcache.writebacks::total 16 # number of writebacks | 424system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu.dcache.fast_writes 0 # number of fast writes performed 431system.cpu.dcache.cache_copies 0 # number of cache copies performed 432system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 433system.cpu.dcache.writebacks::total 16 # number of writebacks |
| 696system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits 697system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits | 434system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits 435system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits |
| 698system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits 699system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits | 436system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 546 # number of WriteReq MSHR hits 437system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits |
| 700system.cpu.dcache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits 701system.cpu.dcache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits 702system.cpu.dcache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits 703system.cpu.dcache.overall_mshr_hits::total 602 # number of overall MSHR hits 704system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses 705system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses | 438system.cpu.dcache.demand_mshr_hits::cpu.inst 626 # number of demand (read+write) MSHR hits 439system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits 440system.cpu.dcache.overall_mshr_hits::cpu.inst 626 # number of overall MSHR hits 441system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits 442system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses 443system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses |
| 706system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses 707system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses | 444system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses 445system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses |
| 708system.cpu.dcache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses 709system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 710system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses 711system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses 712system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles 713system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles 714system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles 715system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles 716system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles 717system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles 718system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles 719system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles | 446system.cpu.dcache.demand_mshr_misses::cpu.inst 1810 # number of demand (read+write) MSHR misses 447system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses 448system.cpu.dcache.overall_mshr_misses::cpu.inst 1810 # number of overall MSHR misses 449system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses 450system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47293264 # number of ReadReq MSHR miss cycles 451system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles 452system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 76493500 # number of WriteReq MSHR miss cycles 453system.cpu.dcache.WriteReq_mshr_miss_latency::total 76493500 # number of WriteReq MSHR miss cycles 454system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 123786764 # number of demand (read+write) MSHR miss cycles 455system.cpu.dcache.demand_mshr_miss_latency::total 123786764 # number of demand (read+write) MSHR miss cycles 456system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 123786764 # number of overall MSHR miss cycles 457system.cpu.dcache.overall_mshr_miss_latency::total 123786764 # number of overall MSHR miss cycles |
| 720system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses 721system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 722system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses 723system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 724system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses 725system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 726system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses 727system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses | 458system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses 459system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 460system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses 461system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 462system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses 463system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 464system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses 465system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses |
| 728system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency 729system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency 730system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency 731system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency 732system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency 733system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency 734system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency 735system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency | 466system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596 # average ReadReq mshr miss latency 467system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency 468system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293 # average WriteReq mshr miss latency 469system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293 # average WriteReq mshr miss latency 470system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency 471system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency 472system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348 # average overall mshr miss latency 473system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348 # average overall mshr miss latency |
| 736system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 474system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 475system.cpu.icache.tags.replacements 2909 # number of replacements 476system.cpu.icache.tags.tagsinuse 1424.880839 # Cycle average of tags in use 477system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. 478system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. 479system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. 480system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 481system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880839 # Average occupied blocks per requestor 482system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy 483system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy 484system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id 485system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 486system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id 487system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id 488system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id 489system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id 490system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id 491system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses 492system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses 493system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits 494system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits 495system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits 496system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits 497system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits 498system.cpu.icache.overall_hits::total 71614329 # number of overall hits 499system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses 500system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses 501system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses 502system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses 503system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses 504system.cpu.icache.overall_misses::total 4706 # number of overall misses 505system.cpu.icache.ReadReq_miss_latency::cpu.inst 186392247 # number of ReadReq miss cycles 506system.cpu.icache.ReadReq_miss_latency::total 186392247 # number of ReadReq miss cycles 507system.cpu.icache.demand_miss_latency::cpu.inst 186392247 # number of demand (read+write) miss cycles 508system.cpu.icache.demand_miss_latency::total 186392247 # number of demand (read+write) miss cycles 509system.cpu.icache.overall_miss_latency::cpu.inst 186392247 # number of overall miss cycles 510system.cpu.icache.overall_miss_latency::total 186392247 # number of overall miss cycles 511system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) 512system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses 514system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses 515system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses 516system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses 517system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 518system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 519system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 520system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 521system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 522system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses 523system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303 # average ReadReq miss latency 524system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303 # average ReadReq miss latency 525system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency 526system.cpu.icache.demand_avg_miss_latency::total 39607.362303 # average overall miss latency 527system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::total 39607.362303 # average overall miss latency 529system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 530system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 531system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 533system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 534system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 535system.cpu.icache.fast_writes 0 # number of fast writes performed 536system.cpu.icache.cache_copies 0 # number of cache copies performed 537system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses 538system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses 539system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses 540system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses 541system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses 542system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses 543system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176061753 # number of ReadReq MSHR miss cycles 544system.cpu.icache.ReadReq_mshr_miss_latency::total 176061753 # number of ReadReq MSHR miss cycles 545system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176061753 # number of demand (read+write) MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::total 176061753 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176061753 # number of overall MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::total 176061753 # number of overall MSHR miss cycles 549system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 550system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 551system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 552system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 553system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 554system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 555system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208 # average ReadReq mshr miss latency 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208 # average ReadReq mshr miss latency 557system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency 559system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency 561system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 562system.cpu.l2cache.tags.replacements 0 # number of replacements 563system.cpu.l2cache.tags.tagsinuse 2001.520468 # Cycle average of tags in use 564system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. 565system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. 566system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. 567system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 568system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor 569system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor 570system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 571system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy 572system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy 573system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id 574system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 575system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 576system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id 577system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id 578system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id 579system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id 580system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses 581system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses 582system.cpu.l2cache.ReadReq_hits::cpu.inst 2623 # number of ReadReq hits 583system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits 584system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits 585system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits 586system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits 587system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 588system.cpu.l2cache.demand_hits::cpu.inst 2631 # number of demand (read+write) hits 589system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits 590system.cpu.l2cache.overall_hits::cpu.inst 2631 # number of overall hits 591system.cpu.l2cache.overall_hits::total 2631 # number of overall hits 592system.cpu.l2cache.ReadReq_misses::cpu.inst 2795 # number of ReadReq misses 593system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses 594system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses 595system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses 596system.cpu.l2cache.demand_misses::cpu.inst 3885 # number of demand (read+write) misses 597system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses 598system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses 599system.cpu.l2cache.overall_misses::total 3885 # number of overall misses 600system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles 602system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles 603system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles 604system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles 605system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles 606system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles 607system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles 608system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) 609system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) 610system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 611system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 614system.cpu.l2cache.demand_accesses::cpu.inst 6516 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 6516 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses 618system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515873 # miss rate for ReadReq accesses 619system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses 621system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses 622system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 # miss rate for demand accesses 623system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses 624system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses 625system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses 626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency 634system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 635system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 638system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu.l2cache.fast_writes 0 # number of fast writes performed 641system.cpu.l2cache.cache_copies 0 # number of cache copies performed 642system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits 643system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 644system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits 645system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 646system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits 647system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 648system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2778 # number of ReadReq MSHR misses 649system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses 650system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses 651system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses 655system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses 656system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles 657system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles 658system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles 659system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles 660system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles 663system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles 664system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses 667system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 668system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses 669system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses 670system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses 671system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency 673system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency 678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency 680system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 681system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution 682system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution 683system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 684system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 685system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 686system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) 687system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) 688system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) 689system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) 690system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) 691system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) 692system.cpu.toL2Bus.snoops 0 # Total snoops (count) 693system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram 694system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 695system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 696system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 697system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 698system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 699system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 700system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 702system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram 703system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 704system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 705system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 706system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 707system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram 708system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) 709system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 710system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks) 711system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 712system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) 713system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 714system.membus.trans_dist::ReadReq 2777 # Transaction distribution 715system.membus.trans_dist::ReadResp 2777 # Transaction distribution 716system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 717system.membus.trans_dist::ReadExResp 1090 # Transaction distribution 718system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) 719system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) 720system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) 721system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) 722system.membus.snoops 0 # Total snoops (count) 723system.membus.snoop_fanout::samples 3867 # Request fanout histogram 724system.membus.snoop_fanout::mean 0 # Request fanout histogram 725system.membus.snoop_fanout::stdev 0 # Request fanout histogram 726system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 727system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram 728system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 729system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 730system.membus.snoop_fanout::min_value 0 # Request fanout histogram 731system.membus.snoop_fanout::max_value 0 # Request fanout histogram 732system.membus.snoop_fanout::total 3867 # Request fanout histogram 733system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) 734system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 735system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks) 736system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
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| 737 738---------- End Simulation Statistics ---------- | 737 738---------- End Simulation Statistics ---------- |