| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.131652 # Number of seconds simulated 4sim_ticks 131652469500 # Number of ticks simulated 5final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.131652 # Number of seconds simulated 4sim_ticks 131652469500 # Number of ticks simulated 5final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 235317 # Simulator instruction rate (inst/s) 8host_op_rate 248063 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 179784828 # Simulator tick rate (ticks/s) 10host_mem_usage 321352 # Number of bytes of host memory used 11host_seconds 732.28 # Real time elapsed on the host | 7host_inst_rate 246188 # Simulator instruction rate (inst/s) 8host_op_rate 259522 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 188090070 # Simulator tick rate (ticks/s) 10host_mem_usage 311300 # Number of bytes of host memory used 11host_seconds 699.94 # Real time elapsed on the host |
| 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory 17system.physmem.bytes_read::total 247616 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory --- 61 unchanged lines hidden (view full) --- 81system.physmem.readPktSize::6 3869 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) | 12sim_insts 172317809 # Number of instructions simulated 13sim_ops 181650742 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory 17system.physmem.bytes_read::total 247616 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory --- 61 unchanged lines hidden (view full) --- 81system.physmem.readPktSize::6 3869 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 89system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see | 89system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see |
| 91system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 91system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 185system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation 199system.physmem.totQLat 27589000 # Total ticks spent queuing 200system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM | 185system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation 199system.physmem.totQLat 27698500 # Total ticks spent queuing 200system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM |
| 201system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers | 201system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers |
| 202system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst | 202system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst | 204system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst |
| 205system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.01 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 205system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.01 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 215system.physmem.readRowHits 2961 # Number of row buffer hits during reads | 215system.physmem.readRowHits 2960 # Number of row buffer hits during reads |
| 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 217system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads | 217system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads |
| 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 34027495.86 # Average gap between requests | 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 34027495.86 # Average gap between requests |
| 220system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states | 220system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states |
| 222system.physmem.memoryStateTime::REF 4396080000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 222system.physmem.memoryStateTime::REF 4396080000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 224system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states | 224system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states |
| 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 226system.membus.throughput 1880831 # Throughput (bytes/s) | |
| 227system.membus.trans_dist::ReadReq 2779 # Transaction distribution 228system.membus.trans_dist::ReadResp 2779 # Transaction distribution 229system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 230system.membus.trans_dist::ReadExResp 1090 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) | 226system.membus.trans_dist::ReadReq 2779 # Transaction distribution 227system.membus.trans_dist::ReadResp 2779 # Transaction distribution 228system.membus.trans_dist::ReadExReq 1090 # Transaction distribution 229system.membus.trans_dist::ReadExResp 1090 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) |
| 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 247616 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 232system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) 233system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) 234system.membus.snoops 0 # Total snoops (count) 235system.membus.snoop_fanout::samples 3869 # Request fanout histogram 236system.membus.snoop_fanout::mean 0 # Request fanout histogram 237system.membus.snoop_fanout::stdev 0 # Request fanout histogram 238system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242system.membus.snoop_fanout::min_value 0 # Request fanout histogram 243system.membus.snoop_fanout::max_value 0 # Request fanout histogram 244system.membus.snoop_fanout::total 3869 # Request fanout histogram |
| 237system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) 238system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 245system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 239system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks) | 247system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks) |
| 240system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 241system.cpu_clk_domain.clock 500 # Clock period in ticks 242system.cpu.branchPred.lookups 49915423 # Number of BP lookups 243system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted 244system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect 245system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups 246system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits 247system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. --- 92 unchanged lines hidden (view full) --- 340system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed 341system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit 342system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 343system.cpu.cpi 1.528019 # CPI: cycles per instruction 344system.cpu.ipc 0.654442 # IPC: instructions per cycle 345system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked 346system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped 347system.cpu.icache.tags.replacements 2881 # number of replacements | 248system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks 250system.cpu.branchPred.lookups 49915423 # Number of BP lookups 251system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect 253system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups 254system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. --- 92 unchanged lines hidden (view full) --- 348system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed 349system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit 350system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 351system.cpu.cpi 1.528019 # CPI: cycles per instruction 352system.cpu.ipc 0.654442 # IPC: instructions per cycle 353system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked 354system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped 355system.cpu.icache.tags.replacements 2881 # number of replacements |
| 348system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use | 356system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use |
| 349system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. 350system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. 351system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. 352system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 357system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. 358system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. 359system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. 360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 353system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor | 361system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor |
| 354system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 369system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits 370system.cpu.icache.overall_hits::total 71509873 # number of overall hits 371system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses 376system.cpu.icache.overall_misses::total 4679 # number of overall misses | 362system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id 369system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id --- 7 unchanged lines hidden (view full) --- 377system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits 378system.cpu.icache.overall_hits::total 71509873 # number of overall hits 379system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses 380system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses 381system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses 382system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses 383system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses 384system.cpu.icache.overall_misses::total 4679 # number of overall misses |
| 377system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles 378system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles 379system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles 380system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles 381system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles 382system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles | 385system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles 386system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles 387system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles 388system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles 389system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles 390system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles |
| 383system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) 385system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses 386system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses 387system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses 388system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses 389system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses 390system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses 391system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses 392system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses 393system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses 394system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses | 391system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) 392system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) 393system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses 394system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses 395system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses 396system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses 397system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses 398system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses 399system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses 400system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses 401system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses 402system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses |
| 395system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency 396system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency 397system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency 398system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency 400system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency | 403system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency 404system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency 405system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency 406system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency 407system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency 408system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency |
| 401system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 402system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 406system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 407system.cpu.icache.fast_writes 0 # number of fast writes performed 408system.cpu.icache.cache_copies 0 # number of cache copies performed 409system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses 410system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses 411system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses 412system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses 413system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses 414system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses | 409system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu.icache.fast_writes 0 # number of fast writes performed 416system.cpu.icache.cache_copies 0 # number of cache copies performed 417system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses 418system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses 419system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses 420system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses 421system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses 422system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses |
| 415system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles 416system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles | 423system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles 424system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles 425system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles 426system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles 427system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles 428system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles |
| 421system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses 422system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses 423system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses 424system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses 425system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses 426system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses | 429system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses 430system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses 431system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses 432system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses 433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses 434system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses |
| 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency | 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency |
| 433system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 441system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 434system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s) | |
| 435system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 440system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) 441system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) | 442system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) |
| 443system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes) 447system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 450system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.snoops 0 # Total snoops (count) 454system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram |
| 448system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) 449system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 450system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) 451system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 452system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) 453system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 454system.cpu.l2cache.tags.replacements 0 # number of replacements | 469system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) 470system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 471system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) 472system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 473system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) 474system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 475system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 455system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use | 476system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use |
| 456system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. 457system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. 458system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. 459system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 460system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor | 477system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. 478system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. 479system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. 480system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 481system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor |
| 461system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor | 482system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor |
| 462system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 484system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses 485system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses 486system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses 487system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses 488system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses 489system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses 490system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses 491system.cpu.l2cache.overall_misses::total 3889 # number of overall misses | 483system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 484system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy 485system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy 486system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id 487system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 488system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id 489system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id 490system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id --- 14 unchanged lines hidden (view full) --- 505system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses 506system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses 507system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses 508system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses 509system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses 510system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses 511system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses 512system.cpu.l2cache.overall_misses::total 3889 # number of overall misses |
| 492system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles 493system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles 494system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles 495system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles 496system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles 497system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles 498system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles 499system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles | 513system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles 514system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles 515system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles 516system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles 517system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles 518system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles 519system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles 520system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles |
| 500system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) 502system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 503system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 506system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses 507system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses 508system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses 509system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses 510system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses 511system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses 512system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses 513system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses 514system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses 515system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses 516system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses 517system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses | 521system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) 522system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) 523system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) 524system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) 526system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) 527system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses 531system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses 532system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses 533system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses 534system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses 535system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses 536system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses 537system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses 538system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses |
| 518system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency 519system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency 520system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency 521system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency 522system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency 523system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency 524system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency 525system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency | 539system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency 540system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency 541system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency 542system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency 543system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency 544system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency 545system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency 546system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency |
| 526system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 532system.cpu.l2cache.fast_writes 0 # number of fast writes performed 533system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 540system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses 541system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses 542system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses 543system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses 544system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses 545system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses 546system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses 547system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses | 547system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.l2cache.fast_writes 0 # number of fast writes performed 554system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 561system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses 562system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses 563system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses 564system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses 565system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses 566system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses 567system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses 568system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses |
| 548system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles 550system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles 551system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles 552system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles 555system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles | 569system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles 570system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles 571system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles 572system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles 573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles 574system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles 575system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles 576system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles |
| 556system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses 558system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses 559system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 560system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses 561system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses 562system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses 563system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses | 577system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses 578system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses 579system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses 580system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses 581system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses 582system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses 583system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses 584system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses |
| 564system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency 565system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency 566system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency 567system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency 568system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency 569system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency 570system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency 571system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency | 585system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency 586system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency 587system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency 588system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency |
| 572system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.dcache.tags.replacements 42 # number of replacements | 593system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu.dcache.tags.replacements 42 # number of replacements |
| 574system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use | 595system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use |
| 575system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. 576system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. 577system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. 578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 596system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. 597system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. 598system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. 599system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 579system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor | 600system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor |
| 580system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy 581system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id 583system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 586system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id 587system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id --- 17 unchanged lines hidden (view full) --- 605system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses 606system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses 607system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses 608system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses 609system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses 610system.cpu.dcache.overall_misses::total 2411 # number of overall misses 611system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles 612system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles | 601system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy 602system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy 603system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id 604system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id 606system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 607system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id --- 17 unchanged lines hidden (view full) --- 626system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses 628system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses 629system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses 630system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses 631system.cpu.dcache.overall_misses::total 2411 # number of overall misses 632system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles 633system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles |
| 613system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles 615system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles 616system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles 617system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles 618system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles | 634system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles 636system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles 637system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles 638system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles 639system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles |
| 619system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) 624system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 625system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) 626system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 633system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses 634system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 635system.cpu.dcache.demand_miss_rate::cpu.inst 0.000059 # miss rate for demand accesses 636system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses 637system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 # miss rate for overall accesses 638system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses 639system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency 640system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency | 640system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) 641system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 22407 # number of LoadLockedReq accesses(hits+misses) 645system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 646system.cpu.dcache.StoreCondReq_accesses::cpu.inst 22407 # number of StoreCondReq accesses(hits+misses) 647system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 654system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000133 # miss rate for WriteReq accesses 655system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 656system.cpu.dcache.demand_miss_rate::cpu.inst 0.000059 # miss rate for demand accesses 657system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses 658system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 # miss rate for overall accesses 659system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses 660system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency 661system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency |
| 641system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency 642system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency 643system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency 644system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency | 662system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency 664system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency 665system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency 666system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency 667system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency |
| 647system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.dcache.fast_writes 0 # number of fast writes performed 654system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 667system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 669system.cpu.dcache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses 670system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 671system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses 672system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses 673system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles | 668system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu.dcache.fast_writes 0 # number of fast writes performed 675system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 688system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1098 # number of WriteReq MSHR misses 689system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses 690system.cpu.dcache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses 691system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses 692system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses 693system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses 694system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles |
| 675system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles 677system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles 680system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles | 696system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles 698system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles 701system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles |
| 681system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 685system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses 686system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 687system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses 688system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency | 702system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses 703system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 704system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses 705system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 706system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for demand accesses 707system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 708system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 # mshr miss rate for overall accesses 709system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses 710system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency 711system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency |
| 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency | 712system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency 713system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency |
| 697system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 698 699---------- End Simulation Statistics ---------- | 718system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 719 720---------- End Simulation Statistics ---------- |