3,5c3,5
< sim_seconds 0.132539 # Number of seconds simulated
< sim_ticks 132538562500 # Number of ticks simulated
< final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.132570 # Number of seconds simulated
> sim_ticks 132570000500 # Number of ticks simulated
> final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 360845 # Simulator instruction rate (inst/s)
< host_op_rate 380389 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 277544932 # Simulator tick rate (ticks/s)
< host_mem_usage 274852 # Number of bytes of host memory used
< host_seconds 477.54 # Real time elapsed on the host
---
> host_inst_rate 373440 # Simulator instruction rate (inst/s)
> host_op_rate 393666 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 287300012 # Simulator tick rate (ticks/s)
> host_mem_usage 274936 # Number of bytes of host memory used
> host_seconds 461.43 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 132538461500 # Total gap between requests
---
> system.physmem.totGap 132569899500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see
192,202c192,202
< system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation
204,205c204,205
< system.physmem.totQLat 84421250 # Total ticks spent queuing
< system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 82551750 # Total ticks spent queuing
> system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst
224c224
< system.physmem.avgGap 34265372.67 # Average gap between requests
---
> system.physmem.avgGap 34273500.39 # Average gap between requests
226,227c226,227
< system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ)
230,246c230,246
< system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ)
< system.physmem_0.averagePower 244.088313 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states
< system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.026270 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states
> system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ)
249,269c249,269
< system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ)
< system.physmem_1.averagePower 243.767063 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 49693791 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits
---
> system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.774090 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 49693872 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target.
274,277c274,277
< system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches.
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 265077125 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 265140001 # number of cpu cycles simulated
406c406
< system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit
408,409c408,409
< system.cpu.cpi 1.538304 # CPI: cycles per instruction
< system.cpu.ipc 0.650067 # IPC: instructions per cycle
---
> system.cpu.cpi 1.538669 # CPI: cycles per instruction
> system.cpu.ipc 0.649913 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
453,454c453,454
< system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks.
456c456
< system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks.
458,460c458,460
< system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy
468,476c468,476
< system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits
481,484c481,484
< system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits
< system.cpu.dcache.overall_hits::total 40710583 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits
> system.cpu.dcache.overall_hits::total 40709647 # number of overall hits
487,488c487,488
< system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses
491,504c491,504
< system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses
< system.cpu.dcache.overall_misses::total 2406 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses
> system.cpu.dcache.overall_misses::total 2405 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses)
507,508c507,508
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses)
513,516c513,516
< system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses
521,522c521,522
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses
527,534c527,534
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency
545,550c545,550
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits
561,564c561,564
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles
567,570c567,570
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles
575,576c575,576
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses
581,584c581,584
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency
587,596c587,596
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 2864 # number of replacements
< system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 2861 # number of replacements
> system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks.
598,600c598,600
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy
603,604c603,604
< system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
608,634c608,634
< system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits
< system.cpu.icache.overall_hits::total 70941363 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses
< system.cpu.icache.overall_misses::total 4664 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 70991309 # number of overall hits
> system.cpu.icache.overall_hits::total 70991309 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses
> system.cpu.icache.overall_misses::total 4661 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 236001500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 70995970 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 70995970 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses
641,646c641,646
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 50718.803602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 50718.803602 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency
653,666c653,666
< system.cpu.icache.writebacks::writebacks 2864 # number of writebacks
< system.cpu.icache.writebacks::total 2864 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4664 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231889500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 231889500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231889500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 231889500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231889500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 231889500 # number of overall MSHR miss cycles
---
> system.cpu.icache.writebacks::writebacks 2861 # number of writebacks
> system.cpu.icache.writebacks::total 2861 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4661 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles
673,679c673,679
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
681,682c681,682
< system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks.
684c684
< system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks.
686,688c686,688
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
693,694c693,694
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id
698,700c698,700
< system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
703,704c703,704
< system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits
---
> system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits
707,708c707,708
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits
---
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits
711c711
< system.cpu.l2cache.demand_hits::cpu.inst 2502 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits
713,714c713,714
< system.cpu.l2cache.demand_hits::total 2590 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2502 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits
716c716
< system.cpu.l2cache.overall_hits::total 2590 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 2587 # number of overall hits
729,740c729,740
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98447500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 98447500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198239500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 198239500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 59270000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 59270000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 198239500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 157717500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 355957000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 198239500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 157717500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 355957000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles
743,744c743,744
< system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses)
747,748c747,748
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4664 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 4664 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses)
751c751
< system.cpu.l2cache.demand_accesses::cpu.inst 4664 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses
753,754c753,754
< system.cpu.l2cache.demand_accesses::total 6475 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4664 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses
756c756
< system.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses
759,760c759,760
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses
763c763
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses
765,766c765,766
< system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses
768,780c768,780
< system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency
809,820c809,820
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles
823,824c823,824
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses
827c827
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses
829,830c829,830
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses
832,846c832,846
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
851,852c851,852
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution
854c854
< system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution
858c858
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution
860c860
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes)
862,863c862,863
< system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes)
865c865
< system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes)
868,870c868,870
< system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram
872,873c872,873
< system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram
878,879c878,879
< system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks)
881c881
< system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks)
891c891
< system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
912c912
< system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks)
914c914
< system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks)
< sim_seconds 0.132539 # Number of seconds simulated
< sim_ticks 132538562500 # Number of ticks simulated
< final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.132570 # Number of seconds simulated
> sim_ticks 132570000500 # Number of ticks simulated
> final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 360845 # Simulator instruction rate (inst/s)
< host_op_rate 380389 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 277544932 # Simulator tick rate (ticks/s)
< host_mem_usage 274852 # Number of bytes of host memory used
< host_seconds 477.54 # Real time elapsed on the host
---
> host_inst_rate 373440 # Simulator instruction rate (inst/s)
> host_op_rate 393666 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 287300012 # Simulator tick rate (ticks/s)
> host_mem_usage 274936 # Number of bytes of host memory used
> host_seconds 461.43 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 132538461500 # Total gap between requests
---
> system.physmem.totGap 132569899500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see
192,202c192,202
< system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation
204,205c204,205
< system.physmem.totQLat 84421250 # Total ticks spent queuing
< system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 82551750 # Total ticks spent queuing
> system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst
224c224
< system.physmem.avgGap 34265372.67 # Average gap between requests
---
> system.physmem.avgGap 34273500.39 # Average gap between requests
226,227c226,227
< system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ)
230,246c230,246
< system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ)
< system.physmem_0.averagePower 244.088313 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states
< system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ)
> system.physmem_0.averagePower 244.026270 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states
> system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ)
249,269c249,269
< system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ)
< system.physmem_1.averagePower 243.767063 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 49693791 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits
---
> system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.774090 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 49693872 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target.
274,277c274,277
< system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches.
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 265077125 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 265140001 # number of cpu cycles simulated
406c406
< system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit
408,409c408,409
< system.cpu.cpi 1.538304 # CPI: cycles per instruction
< system.cpu.ipc 0.650067 # IPC: instructions per cycle
---
> system.cpu.cpi 1.538669 # CPI: cycles per instruction
> system.cpu.ipc 0.649913 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
453,454c453,454
< system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks.
456c456
< system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks.
458,460c458,460
< system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy
468,476c468,476
< system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits
481,484c481,484
< system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits
< system.cpu.dcache.overall_hits::total 40710583 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits
> system.cpu.dcache.overall_hits::total 40709647 # number of overall hits
487,488c487,488
< system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses
491,504c491,504
< system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses
< system.cpu.dcache.overall_misses::total 2406 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses
> system.cpu.dcache.overall_misses::total 2405 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses)
507,508c507,508
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses)
513,516c513,516
< system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses
521,522c521,522
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses
527,534c527,534
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency
545,550c545,550
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits
561,564c561,564
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles
567,570c567,570
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles
575,576c575,576
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses
581,584c581,584
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency
587,596c587,596
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 2864 # number of replacements
< system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 2861 # number of replacements
> system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks.
598,600c598,600
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy
603,604c603,604
< system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
608,634c608,634
< system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits
< system.cpu.icache.overall_hits::total 70941363 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses
< system.cpu.icache.overall_misses::total 4664 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 70991309 # number of overall hits
> system.cpu.icache.overall_hits::total 70991309 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses
> system.cpu.icache.overall_misses::total 4661 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 236001500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 70995970 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 70995970 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses
641,646c641,646
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 50718.803602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 50718.803602 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency
653,666c653,666
< system.cpu.icache.writebacks::writebacks 2864 # number of writebacks
< system.cpu.icache.writebacks::total 2864 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4664 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231889500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 231889500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231889500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 231889500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231889500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 231889500 # number of overall MSHR miss cycles
---
> system.cpu.icache.writebacks::writebacks 2861 # number of writebacks
> system.cpu.icache.writebacks::total 2861 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4661 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles
673,679c673,679
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
681,682c681,682
< system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks.
684c684
< system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks.
686,688c686,688
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
693,694c693,694
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id
698,700c698,700
< system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
703,704c703,704
< system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits
---
> system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits
707,708c707,708
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits
---
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits
711c711
< system.cpu.l2cache.demand_hits::cpu.inst 2502 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits
713,714c713,714
< system.cpu.l2cache.demand_hits::total 2590 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2502 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits
716c716
< system.cpu.l2cache.overall_hits::total 2590 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 2587 # number of overall hits
729,740c729,740
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98447500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 98447500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198239500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 198239500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 59270000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 59270000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 198239500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 157717500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 355957000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 198239500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 157717500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 355957000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles
743,744c743,744
< system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses)
747,748c747,748
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4664 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 4664 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses)
751c751
< system.cpu.l2cache.demand_accesses::cpu.inst 4664 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses
753,754c753,754
< system.cpu.l2cache.demand_accesses::total 6475 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4664 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses
756c756
< system.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses
759,760c759,760
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses
763c763
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses
765,766c765,766
< system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses
768,780c768,780
< system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency
809,820c809,820
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles
823,824c823,824
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses
827c827
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses
829,830c829,830
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses
832,846c832,846
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
851,852c851,852
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution
854c854
< system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution
858c858
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution
860c860
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes)
862,863c862,863
< system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes)
865c865
< system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes)
868,870c868,870
< system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram
872,873c872,873
< system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram
878,879c878,879
< system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks)
881c881
< system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks)
891c891
< system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states
912c912
< system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks)
914c914
< system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks)