3,5c3,5
< sim_seconds 0.132486 # Number of seconds simulated
< sim_ticks 132485848500 # Number of ticks simulated
< final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.132488 # Number of seconds simulated
> sim_ticks 132487590500 # Number of ticks simulated
> final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 159309 # Simulator instruction rate (inst/s)
< host_op_rate 167937 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 122483807 # Simulator tick rate (ticks/s)
< host_mem_usage 270152 # Number of bytes of host memory used
< host_seconds 1081.66 # Real time elapsed on the host
---
> host_inst_rate 200266 # Simulator instruction rate (inst/s)
> host_op_rate 211113 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 153975874 # Simulator tick rate (ticks/s)
> host_mem_usage 275560 # Number of bytes of host memory used
> host_seconds 860.44 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 132485754500 # Total gap between requests
---
> system.physmem.totGap 132487495500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation
< system.physmem.totQLat 30291250 # Total ticks spent queuing
< system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation
> system.physmem.totQLat 28381250 # Total ticks spent queuing
> system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 2934 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2936 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads
224,227c224,227
< system.physmem.avgGap 34251746.25 # Average gap between requests
< system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ)
---
> system.physmem.avgGap 34252196.35 # Average gap between requests
> system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ)
231,235c231,235
< system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.835850 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states
---
> system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.825360 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)
245,249c245,249
< system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.833625 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states
---
> system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.826698 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states
254,256c254,256
< system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 49693791 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 49693795 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted
258c258
< system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups
261,262c261,262
< system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target.
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 264971697 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 264975181 # number of cpu cycles simulated
396c396
< system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit
398,399c398,399
< system.cpu.cpi 1.537692 # CPI: cycles per instruction
< system.cpu.ipc 0.650325 # IPC: instructions per cycle
---
> system.cpu.cpi 1.537712 # CPI: cycles per instruction
> system.cpu.ipc 0.650317 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
439,440c439,440
< system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks.
442c442
< system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks.
444,446c444,446
< system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy
454,458c454,458
< system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits
467,470c467,470
< system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits
< system.cpu.dcache.overall_hits::total 40710586 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits
> system.cpu.dcache.overall_hits::total 40710587 # number of overall hits
481,490c481,490
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses)
499,502c499,502
< system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses
513,520c513,520
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency
547,556c547,556
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles
567,577c567,577
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
579c579
< system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use
584,586c584,586
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy
596c596
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
609,614c609,614
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles
627,632c627,632
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency
647,652c647,652
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles
659,665c659,665
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
667,670c667,670
< system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.
672,688c672,686
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
717,728c715,726
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles
757,768c755,766
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency
797,808c795,806
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles
821,832c819,830
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
839c837
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
873c871,877
< system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
894c898
< system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks)
896c900
< system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks)
< sim_seconds 0.132486 # Number of seconds simulated
< sim_ticks 132485848500 # Number of ticks simulated
< final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.132488 # Number of seconds simulated
> sim_ticks 132487590500 # Number of ticks simulated
> final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 159309 # Simulator instruction rate (inst/s)
< host_op_rate 167937 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 122483807 # Simulator tick rate (ticks/s)
< host_mem_usage 270152 # Number of bytes of host memory used
< host_seconds 1081.66 # Real time elapsed on the host
---
> host_inst_rate 200266 # Simulator instruction rate (inst/s)
> host_op_rate 211113 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 153975874 # Simulator tick rate (ticks/s)
> host_mem_usage 275560 # Number of bytes of host memory used
> host_seconds 860.44 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 132485754500 # Total gap between requests
---
> system.physmem.totGap 132487495500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see
190,205c190,205
< system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation
< system.physmem.totQLat 30291250 # Total ticks spent queuing
< system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation
> system.physmem.totQLat 28381250 # Total ticks spent queuing
> system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst
220c220
< system.physmem.readRowHits 2934 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2936 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads
224,227c224,227
< system.physmem.avgGap 34251746.25 # Average gap between requests
< system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ)
---
> system.physmem.avgGap 34252196.35 # Average gap between requests
> system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ)
231,235c231,235
< system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.835850 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states
---
> system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.825360 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)
245,249c245,249
< system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.833625 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states
---
> system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.826698 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states
254,256c254,256
< system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 49693791 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 49693795 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted
258c258
< system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups
261,262c261,262
< system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target.
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 264971697 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 264975181 # number of cpu cycles simulated
396c396
< system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit
398,399c398,399
< system.cpu.cpi 1.537692 # CPI: cycles per instruction
< system.cpu.ipc 0.650325 # IPC: instructions per cycle
---
> system.cpu.cpi 1.537712 # CPI: cycles per instruction
> system.cpu.ipc 0.650317 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
439,440c439,440
< system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks.
442c442
< system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks.
444,446c444,446
< system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy
454,458c454,458
< system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits
467,470c467,470
< system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits
< system.cpu.dcache.overall_hits::total 40710586 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits
> system.cpu.dcache.overall_hits::total 40710587 # number of overall hits
481,490c481,490
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses)
499,502c499,502
< system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses
513,520c513,520
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency
547,556c547,556
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles
567,577c567,577
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
579c579
< system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use
584,586c584,586
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy
596c596
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
609,614c609,614
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles
627,632c627,632
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency
647,652c647,652
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles
659,665c659,665
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
667,670c667,670
< system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.
672,688c672,686
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
717,728c715,726
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles
757,768c755,766
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency
797,808c795,806
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles
821,832c819,830
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
839c837
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
873c871,877
< system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
894c898
< system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks)
896c900
< system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks)