4,5c4,5
< sim_ticks 130772636500 # Number of ticks simulated
< final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 130772642500 # Number of ticks simulated
> final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 167747 # Simulator instruction rate (inst/s)
< host_op_rate 176832 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 127303889 # Simulator tick rate (ticks/s)
< host_mem_usage 312696 # Number of bytes of host memory used
< host_seconds 1027.25 # Real time elapsed on the host
---
> host_inst_rate 233615 # Simulator instruction rate (inst/s)
> host_op_rate 246267 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 177290947 # Simulator tick rate (ticks/s)
> host_mem_usage 321196 # Number of bytes of host memory used
> host_seconds 737.62 # Real time elapsed on the host
25c25
< system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s)
30c30
< system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 130772543000 # Total gap between requests
---
> system.physmem.totGap 130772548000 # Total gap between requests
93c93
< system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
95c95
< system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
203,204c203,204
< system.physmem.totQLat 28055750 # Total ticks spent queuing
< system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 27654500 # Total ticks spent queuing
> system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst
223c223
< system.physmem.avgGap 33826317.38 # Average gap between requests
---
> system.physmem.avgGap 33826318.68 # Average gap between requests
230,234c230,234
< system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.826718 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states
---
> system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.826558 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states
244,248c244,248
< system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.811822 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states
---
> system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.811714 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states
380c380
< system.cpu.numCycles 261545273 # number of cpu cycles simulated
---
> system.cpu.numCycles 261545285 # number of cpu cycles simulated
389,390c389,390
< system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped
392c392
< system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use
397c397
< system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor
433,440c433,440
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles
465,472c465,472
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency
501,504c501,504
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles
507,510c507,510
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles
521,524c521,524
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency
527,530c527,530
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency
533c533
< system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use
538c538
< system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor
562,567c562,567
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles
580,585c580,585
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency
600,605c600,605
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles
612,617c612,617
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
620c620
< system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use
625,627c625,627
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor
667,678c667,678
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles
705,716c705,716
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency
747,758c747,758
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles
771,782c771,782
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
783a784,789
> system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
799,800c805,806
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram
802,803c808,809
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram
806c812
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
834c840
< system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
836c842
< system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks)
< sim_ticks 130772636500 # Number of ticks simulated
< final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 130772642500 # Number of ticks simulated
> final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 167747 # Simulator instruction rate (inst/s)
< host_op_rate 176832 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 127303889 # Simulator tick rate (ticks/s)
< host_mem_usage 312696 # Number of bytes of host memory used
< host_seconds 1027.25 # Real time elapsed on the host
---
> host_inst_rate 233615 # Simulator instruction rate (inst/s)
> host_op_rate 246267 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 177290947 # Simulator tick rate (ticks/s)
> host_mem_usage 321196 # Number of bytes of host memory used
> host_seconds 737.62 # Real time elapsed on the host
25c25
< system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s)
30c30
< system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 130772543000 # Total gap between requests
---
> system.physmem.totGap 130772548000 # Total gap between requests
93c93
< system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
95c95
< system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
203,204c203,204
< system.physmem.totQLat 28055750 # Total ticks spent queuing
< system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 27654500 # Total ticks spent queuing
> system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst
223c223
< system.physmem.avgGap 33826317.38 # Average gap between requests
---
> system.physmem.avgGap 33826318.68 # Average gap between requests
230,234c230,234
< system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.826718 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states
---
> system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.826558 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states
244,248c244,248
< system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.811822 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states
---
> system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.811714 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states
380c380
< system.cpu.numCycles 261545273 # number of cpu cycles simulated
---
> system.cpu.numCycles 261545285 # number of cpu cycles simulated
389,390c389,390
< system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped
392c392
< system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use
397c397
< system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor
433,440c433,440
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles
465,472c465,472
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency
501,504c501,504
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles
507,510c507,510
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles
521,524c521,524
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency
527,530c527,530
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency
533c533
< system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use
538c538
< system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor
562,567c562,567
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles
580,585c580,585
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency
600,605c600,605
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles
612,617c612,617
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
620c620
< system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use
625,627c625,627
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor
667,678c667,678
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles
705,716c705,716
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency
747,758c747,758
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles
771,782c771,782
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
783a784,789
> system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
799,800c805,806
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram
802,803c808,809
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram
806c812
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
834c840
< system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
836c842
< system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks)