Cross Reference: /gem5/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10827:7f5467f2f8b8 ) new ( 10852:5b58b4cccfd7 )

full compact

3,5c3,5
< sim_seconds 0.131767 # Number of seconds simulated
< sim_ticks 131767151500 # Number of ticks simulated
< final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.131586 # Number of seconds simulated
> sim_ticks 131586268500 # Number of ticks simulated
> final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 244794 # Simulator instruction rate (inst/s)
< host_op_rate 258052 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 187187675 # Simulator tick rate (ticks/s)
< host_mem_usage 317932 # Number of bytes of host memory used
< host_seconds 703.93 # Real time elapsed on the host
---
> host_inst_rate 246297 # Simulator instruction rate (inst/s)
> host_op_rate 259636 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 188078312 # Simulator tick rate (ticks/s)
> host_mem_usage 317920 # Number of bytes of host memory used
> host_seconds 699.64 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 138368 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 247680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 138368 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 138368 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 3869 # Number of read requests accepted
---
> system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 3870 # Number of read requests accepted
34c34
< system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 247680 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 247680 # Total read bytes from the system interface side
48c48
< system.physmem.perBankRdBursts::4 307 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 308 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::11 200 # Per bank write bursts
---
> system.physmem.perBankRdBursts::11 201 # Per bank write bursts
59c59
< system.physmem.perBankRdBursts::15 205 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 204 # Per bank write bursts
78c78
< system.physmem.totGap 131767057000 # Total gap between requests
---
> system.physmem.totGap 131586174000 # Total gap between requests
85c85
< system.physmem.readPktSize::6 3869 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 3870 # Read request sizes (log2)
93,94c93,94
< system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation
< system.physmem.totQLat 28218000 # Total ticks spent queuing
< system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation
> system.physmem.totQLat 26462250 # Total ticks spent queuing
> system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst
219c219
< system.physmem.readRowHits 2961 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2963 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 34057135.44 # Average gap between requests
< system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 34001595.35 # Average gap between requests
> system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.827838 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states
---
> system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.824061 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.799395 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states
---
> system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.792204 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 49934214 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits
---
> system.cpu.branchPred.lookups 49889699 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 263534303 # number of cpu cycles simulated
---
> system.cpu.numCycles 263172537 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.529350 # CPI: cycles per instruction
< system.cpu.ipc 0.653872 # IPC: instructions per cycle
< system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.527251 # CPI: cycles per instruction
> system.cpu.ipc 0.654771 # IPC: instructions per cycle
> system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy
407,410c407,410
< system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 81594514 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits
419,424c419,424
< system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits
< system.cpu.dcache.overall_hits::total 40719565 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits
> system.cpu.dcache.overall_hits::total 40749098 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses
429,442c429,442
< system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses
< system.cpu.dcache.overall_misses::total 2438 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses
> system.cpu.dcache.overall_misses::total 2440 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses)
451,454c451,454
< system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40751073 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40751073 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40751538 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40751538 # number of overall (read+write) accesses
465,472c465,472
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency
483,484c483,484
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
487,490c487,490
< system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
501,504c501,504
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85210500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles
507,510c507,510
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles
521,524c521,524
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency
527,530c527,530
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency
532,536c532,536
< system.cpu.icache.tags.replacements 2892 # number of replacements
< system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2889 # number of replacements
> system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks.
538,540c538,540
< system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy
544,545c544,545
< system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
548,573c548,573
< system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 71598587 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 71598587 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 71598587 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 71598587 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 71598587 # number of overall hits
< system.cpu.icache.overall_hits::total 71598587 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 4691 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 4691 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses
< system.cpu.icache.overall_misses::total 4691 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 200040248 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 200040248 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 200040248 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 200040248 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 71603278 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 71603278 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 71603278 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 71603278 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 71603278 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 71603278 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 143091069 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 143091069 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 71538503 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 71538503 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 71538503 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 71538503 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 71538503 # number of overall hits
> system.cpu.icache.overall_hits::total 71538503 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 4688 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 4688 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 4688 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 4688 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 4688 # number of overall misses
> system.cpu.icache.overall_misses::total 4688 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 200735747 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 200735747 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 200735747 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 200735747 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 200735747 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 200735747 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 71543191 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 71543191 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 71543191 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 71543191 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 71543191 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 71543191 # number of overall (read+write) accesses
580,585c580,585
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 42643.412492 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 42643.412492 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42819.058660 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42819.058660 # average overall miss latency
594,605c594,605
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4691 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4691 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4691 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4691 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192077752 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 192077752 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192077752 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 192077752 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192077752 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 192077752 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4688 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4688 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4688 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192780753 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 192780753 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192780753 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 192780753 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192780753 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 192780753 # number of overall MSHR miss cycles
612,617c612,617
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40946.014069 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40946.014069 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency
620,623c620,623
< system.cpu.l2cache.tags.tagsinuse 2003.582702 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2608 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.935773 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2002.534339 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2603 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2788 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.933644 # Average number of references to valid blocks.
625,627c625,627
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029186 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1509.739376 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814139 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 3.029198 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.688891 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 490.816250 # Average occupied blocks per requestor
629,632c629,632
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046074 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.061144 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046042 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.061112 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 2788 # Occupied blocks per task id
635c635
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id
637,641c637,641
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2007 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 56021 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 56021 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2527 # number of ReadReq hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2006 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085083 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 55998 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 55998 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2522 # number of ReadReq hits
643c643
< system.cpu.l2cache.ReadReq_hits::total 2607 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 2602 # number of ReadReq hits
648c648
< system.cpu.l2cache.demand_hits::cpu.inst 2527 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 2522 # number of demand (read+write) hits
650,651c650,651
< system.cpu.l2cache.demand_hits::total 2615 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2527 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2610 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2522 # number of overall hits
653,654c653,654
< system.cpu.l2cache.overall_hits::total 2615 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 2610 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2166 # number of ReadReq misses
656c656
< system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 2798 # number of ReadReq misses
659c659
< system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 2166 # number of demand (read+write) misses
661,662c661,662
< system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 3888 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2166 # number of overall misses
664,676c664,676
< system.cpu.l2cache.overall_misses::total 3886 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160854250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51424250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 212278500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84027000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 84027000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 160854250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 135451250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 296305500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 160854250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 135451250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 296305500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 4691 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 3888 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161612750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49681750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 211294500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83135500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 83135500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 161612750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 132817250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 294430000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 161612750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 132817250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 294430000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 4688 # number of ReadReq accesses(hits+misses)
678c678
< system.cpu.l2cache.ReadReq_accesses::total 5403 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 5400 # number of ReadReq accesses(hits+misses)
683c683
< system.cpu.l2cache.demand_accesses::cpu.inst 4691 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 4688 # number of demand (read+write) accesses
685,686c685,686
< system.cpu.l2cache.demand_accesses::total 6501 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4691 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 6498 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4688 # number of overall (read+write) accesses
688,689c688,689
< system.cpu.l2cache.overall_accesses::total 6501 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461309 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 6498 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462031 # miss rate for ReadReq accesses
691c691
< system.cpu.l2cache.ReadReq_miss_rate::total 0.517490 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.518148 # miss rate for ReadReq accesses
694c694
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461309 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462031 # miss rate for demand accesses
696,697c696,697
< system.cpu.l2cache.demand_miss_rate::total 0.597754 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461309 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.598338 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462031 # miss rate for overall accesses
699,710c699,710
< system.cpu.l2cache.overall_miss_rate::total 0.597754 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74331.908503 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81367.484177 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75922.210300 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77088.990826 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77088.990826 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74331.908503 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78659.262485 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 76249.485332 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74331.908503 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78659.262485 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 76249.485332 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.598338 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74613.457987 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78610.363924 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75516.261615 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76271.100917 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76271.100917 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75727.880658 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75727.880658 # average overall miss latency
719c719
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
721,722c721,722
< system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
724,725c724,725
< system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
727,728c727,728
< system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2163 # number of ReadReq MSHR misses
730c730
< system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 2781 # number of ReadReq MSHR misses
733c733
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2163 # number of demand (read+write) MSHR misses
735,736c735,736
< system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 3871 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2163 # number of overall MSHR misses
738,750c738,750
< system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 133664500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42488500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176153000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70398000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70398000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 133664500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112886500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 246551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 133664500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112886500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 246551000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 3871 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134379750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40985000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175364750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69507000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69507000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134379750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110492000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 244871750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134379750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110492000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses
752c752
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514529 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses
755c755
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses
757,758c757,758
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.595293 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses
760,771c760,771
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency
773,774c773,774
< system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution
778c778
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes)
780,781c780,781
< system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes)
783c783
< system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes)
785c785
< system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram
790c790
< system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram
795,796c795,796
< system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks)
798c798
< system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks)
802,803c802,803
< system.membus.trans_dist::ReadReq 2779 # Transaction distribution
< system.membus.trans_dist::ReadResp 2779 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 2780 # Transaction distribution
> system.membus.trans_dist::ReadResp 2780 # Transaction distribution
806,809c806,809
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 247680 # Cumulative packet size per connected master and slave (bytes)
811c811
< system.membus.snoop_fanout::samples 3869 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 3870 # Request fanout histogram
815c815
< system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 3870 100.00% 100.00% # Request fanout histogram
820,821c820,821
< system.membus.snoop_fanout::total 3869 # Request fanout histogram
< system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3870 # Request fanout histogram
> system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
823c823
< system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks)