3,5c3,5
< sim_seconds 0.131746 # Number of seconds simulated
< sim_ticks 131745950000 # Number of ticks simulated
< final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.131756 # Number of seconds simulated
> sim_ticks 131756455500 # Number of ticks simulated
> final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 165378 # Simulator instruction rate (inst/s)
< host_op_rate 174335 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 126440065 # Simulator tick rate (ticks/s)
< host_mem_usage 304748 # Number of bytes of host memory used
< host_seconds 1041.96 # Real time elapsed on the host
---
> host_inst_rate 249754 # Simulator instruction rate (inst/s)
> host_op_rate 263281 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 190965456 # Simulator tick rate (ticks/s)
> host_mem_usage 316672 # Number of bytes of host memory used
> host_seconds 689.95 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 247488 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 3867 # Number of read requests accepted
---
> system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 3869 # Number of read requests accepted
34c34
< system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
48c48
< system.physmem.perBankRdBursts::4 308 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 307 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::11 199 # Per bank write bursts
---
> system.physmem.perBankRdBursts::11 201 # Per bank write bursts
59c59
< system.physmem.perBankRdBursts::15 203 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 204 # Per bank write bursts
78c78
< system.physmem.totGap 131745861500 # Total gap between requests
---
> system.physmem.totGap 131756361000 # Total gap between requests
85c85
< system.physmem.readPktSize::6 3867 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 3869 # Read request sizes (log2)
93c93
< system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation
< system.physmem.totQLat 28130750 # Total ticks spent queuing
< system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation
> system.physmem.totQLat 26801000 # Total ticks spent queuing
> system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst
219c219
< system.physmem.readRowHits 2950 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2968 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 34069268.55 # Average gap between requests
< system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 34054370.90 # Average gap between requests
> system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.807422 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states
---
> system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.773044 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.815773 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states
---
> system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.806861 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 49935043 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits
---
> system.cpu.branchPred.lookups 49934480 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 263491900 # number of cpu cycles simulated
---
> system.cpu.numCycles 263512911 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.529104 # CPI: cycles per instruction
< system.cpu.ipc 0.653978 # IPC: instructions per cycle
< system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.529226 # CPI: cycles per instruction
> system.cpu.ipc 0.653925 # IPC: instructions per cycle
> system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
407,412c407,412
< system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
417,424c417,424
< system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits
< system.cpu.dcache.overall_hits::total 40718173 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits
> system.cpu.dcache.overall_hits::total 40720863 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
429,438c429,438
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses)
445,448c445,448
< system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses
457,464c457,464
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency
475,478c475,478
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
491,498c491,498
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles
507,514c507,514
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
516,520c516,520
< system.cpu.icache.tags.replacements 2909 # number of replacements
< system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2891 # number of replacements
> system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks.
522,525c522,525
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
528,569c528,569
< system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits
< system.cpu.icache.overall_hits::total 71614329 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses
< system.cpu.icache.overall_misses::total 4706 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits
> system.cpu.icache.overall_hits::total 71597357 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses
> system.cpu.icache.overall_misses::total 4689 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency
578,601c578,601
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
604,607c604,607
< system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks.
609,611c609,611
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor
613,614c613,614
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy
616,620c616,620
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
622,625c622,625
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits
627c627
< system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits
632c632
< system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits
634,635c634,635
< system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits
637,638c637,638
< system.cpu.l2cache.overall_hits::total 2631 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 2613 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses
640c640
< system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses
643c643
< system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses
645,646c645,646
< system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses
648,660c648,660
< system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 3886 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses)
662c662
< system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses)
667c667
< system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses
669,670c669,670
< system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses
672,673c672,673
< system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses
675c675
< system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses
678c678
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses
680,681c680,681
< system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses
683,694c683,694
< system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency
703c703
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
705,706c705,706
< system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
708,709c708,709
< system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
711,712c711,712
< system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses
714c714
< system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses
717c717
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses
719,720c719,720
< system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses
722,734c722,734
< system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses
736c736
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses
739c739
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses
741,742c741,742
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses
744,755c744,755
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
757,758c757,758
< system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution
762c762
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes)
764,765c764,765
< system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes)
767c767
< system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes)
769,770c769,770
< system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
776,779c776,777
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
781,784c779,782
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks)
786c784
< system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks)
788c786
< system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks)
790,791c788,789
< system.membus.trans_dist::ReadReq 2777 # Transaction distribution
< system.membus.trans_dist::ReadResp 2777 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 2779 # Transaction distribution
> system.membus.trans_dist::ReadResp 2779 # Transaction distribution
794,797c792,795
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
799c797
< system.membus.snoop_fanout::samples 3867 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 3869 # Request fanout histogram
803c801
< system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
808,809c806,807
< system.membus.snoop_fanout::total 3867 # Request fanout histogram
< system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3869 # Request fanout histogram
> system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks)
811c809
< system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks)
< sim_seconds 0.131746 # Number of seconds simulated
< sim_ticks 131745950000 # Number of ticks simulated
< final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.131756 # Number of seconds simulated
> sim_ticks 131756455500 # Number of ticks simulated
> final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 165378 # Simulator instruction rate (inst/s)
< host_op_rate 174335 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 126440065 # Simulator tick rate (ticks/s)
< host_mem_usage 304748 # Number of bytes of host memory used
< host_seconds 1041.96 # Real time elapsed on the host
---
> host_inst_rate 249754 # Simulator instruction rate (inst/s)
> host_op_rate 263281 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 190965456 # Simulator tick rate (ticks/s)
> host_mem_usage 316672 # Number of bytes of host memory used
> host_seconds 689.95 # Real time elapsed on the host
16c16
< system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
18,21c18,21
< system.physmem.bytes_read::total 247488 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
23,32c23,32
< system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 3867 # Number of read requests accepted
---
> system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 3869 # Number of read requests accepted
34c34
< system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
36c36
< system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
39c39
< system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
48c48
< system.physmem.perBankRdBursts::4 308 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 307 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::11 199 # Per bank write bursts
---
> system.physmem.perBankRdBursts::11 201 # Per bank write bursts
59c59
< system.physmem.perBankRdBursts::15 203 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 204 # Per bank write bursts
78c78
< system.physmem.totGap 131745861500 # Total gap between requests
---
> system.physmem.totGap 131756361000 # Total gap between requests
85c85
< system.physmem.readPktSize::6 3867 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 3869 # Read request sizes (log2)
93c93
< system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see
189,206c189,206
< system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation
< system.physmem.totQLat 28130750 # Total ticks spent queuing
< system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation
> system.physmem.totQLat 26801000 # Total ticks spent queuing
> system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst
219c219
< system.physmem.readRowHits 2950 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2968 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads
223,227c223,227
< system.physmem.avgGap 34069268.55 # Average gap between requests
< system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 34054370.90 # Average gap between requests
> system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ)
229,235c229,235
< system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.807422 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states
---
> system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.773044 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ)
243,249c243,249
< system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.815773 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states
---
> system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.806861 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 49935043 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits
---
> system.cpu.branchPred.lookups 49934480 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target.
380c380
< system.cpu.numCycles 263491900 # number of cpu cycles simulated
---
> system.cpu.numCycles 263512911 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 1.529104 # CPI: cycles per instruction
< system.cpu.ipc 0.653978 # IPC: instructions per cycle
< system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.529226 # CPI: cycles per instruction
> system.cpu.ipc 0.653925 # IPC: instructions per cycle
> system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
401,402c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
407,412c407,412
< system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
417,424c417,424
< system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits
< system.cpu.dcache.overall_hits::total 40718173 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits
> system.cpu.dcache.overall_hits::total 40720863 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
429,438c429,438
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses)
445,448c445,448
< system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses
457,464c457,464
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency
475,478c475,478
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
491,498c491,498
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles
507,514c507,514
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
516,520c516,520
< system.cpu.icache.tags.replacements 2909 # number of replacements
< system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 2891 # number of replacements
> system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks.
522,525c522,525
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
528,569c528,569
< system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits
< system.cpu.icache.overall_hits::total 71614329 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses
< system.cpu.icache.overall_misses::total 4706 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits
> system.cpu.icache.overall_hits::total 71597357 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses
> system.cpu.icache.overall_misses::total 4689 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency
578,601c578,601
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
604,607c604,607
< system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks.
609,611c609,611
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor
613,614c613,614
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy
616,620c616,620
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
622,625c622,625
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits
627c627
< system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits
632c632
< system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits
634,635c634,635
< system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits
637,638c637,638
< system.cpu.l2cache.overall_hits::total 2631 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 2613 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses
640c640
< system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses
643c643
< system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses
645,646c645,646
< system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses
648,660c648,660
< system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 3886 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses)
662c662
< system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses)
667c667
< system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses
669,670c669,670
< system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses
672,673c672,673
< system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses
675c675
< system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses
678c678
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses
680,681c680,681
< system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses
683,694c683,694
< system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency
703c703
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
705,706c705,706
< system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
708,709c708,709
< system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
711,712c711,712
< system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses
714c714
< system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses
717c717
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses
719,720c719,720
< system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses
722,734c722,734
< system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses
736c736
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses
739c739
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses
741,742c741,742
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses
744,755c744,755
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
757,758c757,758
< system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution
762c762
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes)
764,765c764,765
< system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes)
767c767
< system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes)
769,770c769,770
< system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
776,779c776,777
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
781,784c779,782
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks)
786c784
< system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks)
788c786
< system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks)
790,791c788,789
< system.membus.trans_dist::ReadReq 2777 # Transaction distribution
< system.membus.trans_dist::ReadResp 2777 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 2779 # Transaction distribution
> system.membus.trans_dist::ReadResp 2779 # Transaction distribution
794,797c792,795
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
799c797
< system.membus.snoop_fanout::samples 3867 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 3869 # Request fanout histogram
803c801
< system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
808,809c806,807
< system.membus.snoop_fanout::total 3867 # Request fanout histogram
< system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3869 # Request fanout histogram
> system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks)
811c809
< system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks)