7,11c7,11
< host_inst_rate 235317 # Simulator instruction rate (inst/s)
< host_op_rate 248063 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 179784828 # Simulator tick rate (ticks/s)
< host_mem_usage 321352 # Number of bytes of host memory used
< host_seconds 732.28 # Real time elapsed on the host
---
> host_inst_rate 246188 # Simulator instruction rate (inst/s)
> host_op_rate 259522 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 188090070 # Simulator tick rate (ticks/s)
> host_mem_usage 311300 # Number of bytes of host memory used
> host_seconds 699.94 # Real time elapsed on the host
89,90c89,90
< system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see
185,200c185,200
< system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation
< system.physmem.totQLat 27589000 # Total ticks spent queuing
< system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation
> system.physmem.totQLat 27698500 # Total ticks spent queuing
> system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst
204c204
< system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst
215c215
< system.physmem.readRowHits 2961 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2960 # Number of row buffer hits during reads
217c217
< system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads
220,221c220,221
< system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states
---
> system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states
224c224
< system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states
226d225
< system.membus.throughput 1880831 # Throughput (bytes/s)
233,236c232,244
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 247616 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 3869 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 3869 # Request fanout histogram
239c247
< system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks)
348c356
< system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use
353c361
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor
377,382c385,390
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles
395,400c403,408
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency
415,420c423,428
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles
427,432c435,440
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
434d441
< system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s)
443,447c450,468
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram
455c476
< system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use
461c482
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor
492,499c513,520
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles
518,525c539,546
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency
548,555c569,576
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles
564,571c585,592
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
574c595
< system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use
579c600
< system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor
613,618c634,639
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles
641,646c662,667
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency
675,680c696,701
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles
691,696c712,717
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
< host_inst_rate 235317 # Simulator instruction rate (inst/s)
< host_op_rate 248063 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 179784828 # Simulator tick rate (ticks/s)
< host_mem_usage 321352 # Number of bytes of host memory used
< host_seconds 732.28 # Real time elapsed on the host
---
> host_inst_rate 246188 # Simulator instruction rate (inst/s)
> host_op_rate 259522 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 188090070 # Simulator tick rate (ticks/s)
> host_mem_usage 311300 # Number of bytes of host memory used
> host_seconds 699.94 # Real time elapsed on the host
89,90c89,90
< system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see
185,200c185,200
< system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation
< system.physmem.totQLat 27589000 # Total ticks spent queuing
< system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation
> system.physmem.totQLat 27698500 # Total ticks spent queuing
> system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst
204c204
< system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst
215c215
< system.physmem.readRowHits 2961 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 2960 # Number of row buffer hits during reads
217c217
< system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads
220,221c220,221
< system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states
---
> system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states
224c224
< system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states
226d225
< system.membus.throughput 1880831 # Throughput (bytes/s)
233,236c232,244
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 247616 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 3869 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 3869 # Request fanout histogram
239c247
< system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks)
348c356
< system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use
353c361
< system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor
377,382c385,390
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles
395,400c403,408
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency
415,420c423,428
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles
427,432c435,440
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
434d441
< system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s)
443,447c450,468
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram
455c476
< system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use
461c482
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor
492,499c513,520
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles
518,525c539,546
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency
548,555c569,576
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles
564,571c585,592
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
574c595
< system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use
579c600
< system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor
613,618c634,639
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles
641,646c662,667
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency
675,680c696,701
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles
691,696c712,717
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency