Cross Reference: /gem5/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.132486 # Number of seconds simulated
4sim_ticks 132485848500 # Number of ticks simulated
5final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.132488 # Number of seconds simulated
4sim_ticks 132487590500 # Number of ticks simulated
5final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 159309 # Simulator instruction rate (inst/s)
8host_op_rate 167937 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 122483807 # Simulator tick rate (ticks/s)
10host_mem_usage 270152 # Number of bytes of host memory used
11host_seconds 1081.66 # Real time elapsed on the host

7host_inst_rate 200266 # Simulator instruction rate (inst/s)
8host_op_rate 211113 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 153975874 # Simulator tick rate (ticks/s)
10host_mem_usage 275560 # Number of bytes of host memory used
11host_seconds 860.44 # Real time elapsed on the host

12sim_insts 172317810 # Number of instructions simulated
13sim_ops 181650743 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
19system.physmem.bytes_read::total 247552 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory

25system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s)

25system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s)

33system.physmem.readReqs 3868 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 247552 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 305 # Per bank write bursts
46system.physmem.perBankRdBursts::1 217 # Per bank write bursts
47system.physmem.perBankRdBursts::2 135 # Per bank write bursts
48system.physmem.perBankRdBursts::3 313 # Per bank write bursts
49system.physmem.perBankRdBursts::4 306 # Per bank write bursts
50system.physmem.perBankRdBursts::5 305 # Per bank write bursts
51system.physmem.perBankRdBursts::6 273 # Per bank write bursts
52system.physmem.perBankRdBursts::7 222 # Per bank write bursts
53system.physmem.perBankRdBursts::8 248 # Per bank write bursts
54system.physmem.perBankRdBursts::9 218 # Per bank write bursts
55system.physmem.perBankRdBursts::10 296 # Per bank write bursts
56system.physmem.perBankRdBursts::11 200 # Per bank write bursts
57system.physmem.perBankRdBursts::12 183 # Per bank write bursts
58system.physmem.perBankRdBursts::13 218 # Per bank write bursts
59system.physmem.perBankRdBursts::14 224 # Per bank write bursts
60system.physmem.perBankRdBursts::15 205 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

79system.physmem.totGap 132485754500 # Total gap between requests

79system.physmem.totGap 132487495500 # Total gap between requests

80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 3868 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)

94system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see

94system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see

96system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see

190system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation
204system.physmem.totQLat 30291250 # Total ticks spent queuing
205system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM

190system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation
204system.physmem.totQLat 28381250 # Total ticks spent queuing
205system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM

206system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers

207system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst

207system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst

208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

209system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst

209system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst

210system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 0.01 # Data bus utilization in percentage
216system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing

220system.physmem.readRowHits 2934 # Number of row buffer hits during reads

220system.physmem.readRowHits 2936 # Number of row buffer hits during reads

221system.physmem.writeRowHits 0 # Number of row buffer hits during writes

222system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads

222system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads

223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

224system.physmem.avgGap 34251746.25 # Average gap between requests
225system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ)

224system.physmem.avgGap 34252196.35 # Average gap between requests
225system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ)

228system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ)

231system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ)
233system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ)
234system.physmem_0.averagePower 668.835850 # Core power per rank (mW)
235system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states

231system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ)
233system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ)
234system.physmem_0.averagePower 668.825360 # Core power per rank (mW)
235system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states

236system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states
237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

238system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states

238system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states

239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states

240system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ)
241system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ)
242system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)

240system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ)
241system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ)
242system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)

243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
244system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ)

245system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ)
246system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ)
247system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ)
248system.physmem_1.averagePower 668.833625 # Core power per rank (mW)
249system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states

245system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ)
246system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ)
247system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ)
248system.physmem_1.averagePower 668.826698 # Core power per rank (mW)
249system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states

250system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states
251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

252system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states

252system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states

253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

254system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
255system.cpu.branchPred.lookups 49693791 # Number of BP lookups
256system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted

254system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
255system.cpu.branchPred.lookups 49693795 # Number of BP lookups
256system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted

257system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect

258system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups

258system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups

259system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits
260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

261system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
262system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.

261system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage
262system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target.

263system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
264system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups.
265system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits.
266system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses.
267system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches.
268system.cpu_clk_domain.clock 500 # Clock period in ticks

269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
278system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
279system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
280system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
281system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
282system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
283system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
288system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
289system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
290system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

300system.cpu.dtb.walker.walks 0 # Table walker walks requested
301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
308system.cpu.dtb.inst_hits 0 # ITB inst hits
309system.cpu.dtb.inst_misses 0 # ITB inst misses
310system.cpu.dtb.read_hits 0 # DTB read hits
311system.cpu.dtb.read_misses 0 # DTB read misses
312system.cpu.dtb.write_hits 0 # DTB write hits
313system.cpu.dtb.write_misses 0 # DTB write misses
314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
316system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
317system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
318system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
320system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
323system.cpu.dtb.read_accesses 0 # DTB read accesses
324system.cpu.dtb.write_accesses 0 # DTB write accesses
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
326system.cpu.dtb.hits 0 # DTB hits
327system.cpu.dtb.misses 0 # DTB misses
328system.cpu.dtb.accesses 0 # DTB accesses

329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
338system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
339system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
340system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
341system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
342system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
343system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
344system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
346system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
347system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
348system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
349system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
350system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

360system.cpu.itb.walker.walks 0 # Table walker walks requested
361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
368system.cpu.itb.inst_hits 0 # ITB inst hits
369system.cpu.itb.inst_misses 0 # ITB inst misses
370system.cpu.itb.read_hits 0 # DTB read hits
371system.cpu.itb.read_misses 0 # DTB read misses
372system.cpu.itb.write_hits 0 # DTB write hits
373system.cpu.itb.write_misses 0 # DTB write misses
374system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
375system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
376system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
377system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
378system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
379system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
380system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
381system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
383system.cpu.itb.read_accesses 0 # DTB read accesses
384system.cpu.itb.write_accesses 0 # DTB write accesses
385system.cpu.itb.inst_accesses 0 # ITB inst accesses
386system.cpu.itb.hits 0 # DTB hits
387system.cpu.itb.misses 0 # DTB misses
388system.cpu.itb.accesses 0 # DTB accesses
389system.cpu.workload.num_syscalls 400 # Number of system calls

390system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states
391system.cpu.numCycles 264971697 # number of cpu cycles simulated

390system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states
391system.cpu.numCycles 264975181 # number of cpu cycles simulated

392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
394system.cpu.committedInsts 172317810 # Number of instructions committed
395system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed

396system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit

396system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit

397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching

398system.cpu.cpi 1.537692 # CPI: cycles per instruction
399system.cpu.ipc 0.650325 # IPC: instructions per cycle

398system.cpu.cpi 1.537712 # CPI: cycles per instruction
399system.cpu.ipc 0.650317 # IPC: instructions per cycle

400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
401system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
402system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
403system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
404system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
405system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
406system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
407system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
408system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
409system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
410system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
411system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
412system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
413system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
414system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
415system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
416system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
417system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
418system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
419system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
420system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
421system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
422system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
423system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
424system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
425system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
426system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
427system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
428system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
429system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
430system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
431system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
434system.cpu.op_class_0::total 181650743 # Class of committed instruction

435system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked
436system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped
437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

435system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked
436system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped
437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

438system.cpu.dcache.tags.replacements 42 # number of replacements

439system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use
440system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks.

439system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use
440system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks.

441system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.

442system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks.

442system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks.

443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

444system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor
445system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy
446system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy

444system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor
445system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy
446system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy

447system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
448system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
449system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
450system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
451system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
452system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
453system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id

454system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
455system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
456system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
457system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
458system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits

454system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses
455system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses
456system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
457system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits
458system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits

459system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits
460system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits
461system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
462system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
463system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
464system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
465system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
466system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits

467system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits
468system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits
469system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits
470system.cpu.dcache.overall_hits::total 40710586 # number of overall hits

467system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits
468system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits
469system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits
470system.cpu.dcache.overall_hits::total 40710587 # number of overall hits

471system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses
472system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses
473system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses
474system.cpu.dcache.WriteReq_misses::total 1651 # number of WriteReq misses
475system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
476system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
477system.cpu.dcache.demand_misses::cpu.data 2402 # number of demand (read+write) misses
478system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses
479system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses
480system.cpu.dcache.overall_misses::total 2403 # number of overall misses

481system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles
482system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles
483system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles
484system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles
485system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles
486system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles
487system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles
488system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles
489system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
490system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)

481system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles
482system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles
483system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles
484system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles
485system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles
486system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles
487system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles
488system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles
489system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses)
490system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses)

491system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
492system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
493system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
494system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
496system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
497system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
498system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)

499system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
500system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
501system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
502system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses

499system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses
500system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses
501system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses
502system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses

503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
504system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses
506system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses
507system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
508system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
509system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses
510system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses
511system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses
512system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses

513system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency
514system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency
515system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency
516system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency
517system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency
518system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency
519system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency
520system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency

513system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency
514system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency
515system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency
516system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency
517system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency
518system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency
519system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency
520system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency

521system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
522system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
523system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
524system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
525system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
526system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
527system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
528system.cpu.dcache.writebacks::total 16 # number of writebacks
529system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
530system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
531system.cpu.dcache.WriteReq_mshr_hits::cpu.data 552 # number of WriteReq MSHR hits
532system.cpu.dcache.WriteReq_mshr_hits::total 552 # number of WriteReq MSHR hits
533system.cpu.dcache.demand_mshr_hits::cpu.data 592 # number of demand (read+write) MSHR hits
534system.cpu.dcache.demand_mshr_hits::total 592 # number of demand (read+write) MSHR hits
535system.cpu.dcache.overall_mshr_hits::cpu.data 592 # number of overall MSHR hits
536system.cpu.dcache.overall_mshr_hits::total 592 # number of overall MSHR hits
537system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
538system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
539system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
540system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses
541system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
542system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
543system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
544system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
545system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
546system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses

547system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles
548system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles
549system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles
550system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles
551system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
552system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
553system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles
554system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles
555system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles
556system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles

547system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles
548system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles
549system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles
550system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles
551system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles
552system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles
553system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles
554system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles
555system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles
556system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles

557system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
558system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
559system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
560system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
561system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
562system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
563system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
564system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
565system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
566system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses

567system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency
568system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency
569system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency
570system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency
571system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
572system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
573system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency
574system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency
575system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency
576system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency
577system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

567system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency
568system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency
569system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency
570system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency
571system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency
572system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency
573system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency
574system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency
575system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency
576system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency
577system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

578system.cpu.icache.tags.replacements 2864 # number of replacements

579system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use

579system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use

580system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks.
581system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks.
582system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks.
583system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

584system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor
585system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy
586system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy

584system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor
585system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy
586system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy

587system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id
588system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
589system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
590system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
591system.cpu.icache.tags.age_task_id_blocks_1024::3 130 # Occupied blocks per task id
592system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
593system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id
594system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses
595system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses

596system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

596system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

597system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits
598system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits
599system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits
600system.cpu.icache.demand_hits::total 70941364 # number of demand (read+write) hits
601system.cpu.icache.overall_hits::cpu.inst 70941364 # number of overall hits
602system.cpu.icache.overall_hits::total 70941364 # number of overall hits
603system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses
604system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses
605system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses
606system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses
607system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses
608system.cpu.icache.overall_misses::total 4664 # number of overall misses

609system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles
610system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles
611system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles
612system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles
613system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles
614system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles

609system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles
610system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles
611system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles
612system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles
613system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles
614system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles

615system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses)
616system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses)
617system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses
618system.cpu.icache.demand_accesses::total 70946028 # number of demand (read+write) accesses
619system.cpu.icache.overall_accesses::cpu.inst 70946028 # number of overall (read+write) accesses
620system.cpu.icache.overall_accesses::total 70946028 # number of overall (read+write) accesses
621system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
622system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
623system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
624system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
625system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
626system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses

627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency
628system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency
629system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
630system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency
631system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
632system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency

627system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency
628system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency
629system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
630system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency
631system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
632system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency

633system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
634system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
635system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
636system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
637system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
638system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
639system.cpu.icache.writebacks::writebacks 2864 # number of writebacks
640system.cpu.icache.writebacks::total 2864 # number of writebacks
641system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses
642system.cpu.icache.ReadReq_mshr_misses::total 4664 # number of ReadReq MSHR misses
643system.cpu.icache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses
644system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses
645system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
646system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses

647system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles
648system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles
649system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles
650system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles
651system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles
652system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles

647system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles
648system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles
649system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles
650system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles
651system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles
652system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles

653system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
654system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
655system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
656system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
658system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses

659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency
660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency
661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
662system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
664system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
665system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency
660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency
661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
662system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
664system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
665system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

666system.cpu.l2cache.tags.replacements 0 # number of replacements

667system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use
668system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks.
669system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
670system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks.

667system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use
668system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
669system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
670system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.

671system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

672system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor
673system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor
674system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor
675system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
676system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy
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680system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
681system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
682system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
683system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id
684system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id
685system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
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687system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses
688system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

672system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor
673system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor
674system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
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676system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy
677system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
678system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
679system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
680system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id
681system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id
682system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
683system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
684system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
685system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
686system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

689system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
690system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
691system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits
692system.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits
693system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
694system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
695system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits
696system.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits
697system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
698system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
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700system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
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703system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
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706system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
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708system.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses
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710system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
711system.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses
712system.cpu.l2cache.demand_misses::cpu.data 1723 # number of demand (read+write) misses
713system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
714system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses
715system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses
716system.cpu.l2cache.overall_misses::total 3885 # number of overall misses

687system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
688system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
689system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits
690system.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits
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692system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
693system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits
694system.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits
695system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
696system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
697system.cpu.l2cache.demand_hits::cpu.inst 2502 # number of demand (read+write) hits
698system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
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701system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
702system.cpu.l2cache.overall_hits::total 2590 # number of overall hits
703system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
704system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
705system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses
706system.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses
707system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
708system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
709system.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses
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713system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses
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727system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles
728system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles

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717system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles
718system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles
719system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles
720system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles
721system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles
722system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles
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724system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles
725system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles
726system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles

729system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
730system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
731system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses)
732system.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses)
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743system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
744system.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses
745system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
746system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
747system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses
748system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses
749system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
750system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses
751system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses
752system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses
753system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses
754system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses
755system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses
756system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses

727system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
728system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
729system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses)
730system.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses)
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732system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
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734system.cpu.l2cache.ReadCleanReq_accesses::total 4664 # number of ReadCleanReq accesses(hits+misses)
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744system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
745system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses
746system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses
747system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
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757system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency
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759system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency
760system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency
761system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency
762system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency
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764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
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767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
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755system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency
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757system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency
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759system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency
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765system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
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783system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
784system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
785system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
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795system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
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786system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses
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798system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles
799system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles
800system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles
801system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles
802system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles
803system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles
804system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles
805system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles
806system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles
807system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles
808system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles

795system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles
796system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles
797system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles
798system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles
799system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles
800system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles
801system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles
802system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles
803system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles
804system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles
805system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles
806system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles

809system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
810system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
811system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses
812system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses
813system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
814system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
815system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses
816system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
817system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses
818system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses
819system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
820system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses

807system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
808system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
809system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses
810system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses
811system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
812system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
813system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses
814system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
815system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses
816system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses
817system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
818system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses

821system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency
822system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency
823system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency
824system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency
825system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency
826system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency
827system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
828system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
829system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
830system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
831system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
832system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency

819system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency
820system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency
821system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency
822system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency
823system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency
824system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency
825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
826system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
827system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
829system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
830system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency

833system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter.
834system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
835system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
836system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
837system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
838system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

831system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter.
832system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
833system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
834system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
835system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
836system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

839system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

837system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

840system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution
841system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
842system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution
843system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
844system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
845system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
846system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution
847system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
848system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes)
849system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
850system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes)
851system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes)
852system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
853system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes)
854system.cpu.toL2Bus.snoops 0 # Total snoops (count)
855system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
856system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram
857system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram
858system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram
859system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
860system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram
861system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram
862system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
863system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
864system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
865system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
866system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram
867system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks)
868system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
869system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks)
870system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
871system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks)
872system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

838system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution
839system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
840system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution
841system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
842system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
843system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
844system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution
845system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
846system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes)
847system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
848system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes)
849system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes)
850system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
851system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes)
852system.cpu.toL2Bus.snoops 0 # Total snoops (count)
853system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
854system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram
855system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram
856system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram
857system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
858system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram
859system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram
860system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
861system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
862system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
863system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
864system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram
865system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks)
866system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
867system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks)
868system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
869system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks)
870system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

873system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states

871system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter.
872system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
873system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
874system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
875system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
876system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
877system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states

874system.membus.trans_dist::ReadResp 2777 # Transaction distribution
875system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
876system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
877system.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution
878system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes)
879system.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes)
880system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes)
881system.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes)
882system.membus.snoops 0 # Total snoops (count)
883system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
884system.membus.snoop_fanout::samples 3868 # Request fanout histogram
885system.membus.snoop_fanout::mean 0 # Request fanout histogram
886system.membus.snoop_fanout::stdev 0 # Request fanout histogram
887system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
888system.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram
889system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
890system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
891system.membus.snoop_fanout::min_value 0 # Request fanout histogram
892system.membus.snoop_fanout::max_value 0 # Request fanout histogram
893system.membus.snoop_fanout::total 3868 # Request fanout histogram

878system.membus.trans_dist::ReadResp 2777 # Transaction distribution
879system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
880system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
881system.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution
882system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes)
883system.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes)
884system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes)
885system.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes)
886system.membus.snoops 0 # Total snoops (count)
887system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
888system.membus.snoop_fanout::samples 3868 # Request fanout histogram
889system.membus.snoop_fanout::mean 0 # Request fanout histogram
890system.membus.snoop_fanout::stdev 0 # Request fanout histogram
891system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
892system.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram
893system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
894system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
895system.membus.snoop_fanout::min_value 0 # Request fanout histogram
896system.membus.snoop_fanout::max_value 0 # Request fanout histogram
897system.membus.snoop_fanout::total 3868 # Request fanout histogram

894system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)

898system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks)

895system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

899system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

896system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks)

900system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks)