| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
| 18eventq_index=0 |
| 19exit_on_work_items=false |
| 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false |
| 29multi_thread=false |
| 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
| 35readfile= 36symbolfile= |
| 37thermal_components= 38thermal_model=Null |
| 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] --- 12 unchanged lines hidden (view full) --- 59branchPred=system.cpu.branchPred 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63decodeCycleInput=true 64decodeInputBufferSize=3 65decodeInputWidth=2 66decodeToExecuteForwardDelay=1 |
| 67default_p_state=UNDEFINED |
| 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73enableIdling=true 74eventq_index=0 75executeAllowEarlyMemoryIssue=true --- 28 unchanged lines hidden (view full) --- 104isa=system.cpu.isa 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111numThreads=1 |
| 112p_state_clk_gate_bins=20 113p_state_clk_gate_max=1000000000000 114p_state_clk_gate_min=1000 115power_model=Null |
| 116profile=0 117progress_interval=0 118simpoint_start_insts= 119socket_id=0 120switched_out=false 121system=system |
| 122threadPolicy=RoundRobin |
| 123tracer=system.cpu.tracer 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.branchPred] 129type=TournamentBP 130BTBEntries=4096 131BTBTagSize=16 132RASSize=16 133choiceCtrBits=2 134choicePredictorSize=8192 135eventq_index=0 136globalCtrBits=2 137globalPredictorSize=8192 |
| 138indirectHashGHR=true 139indirectHashTargets=true 140indirectPathLength=3 141indirectSets=256 142indirectTagSize=16 143indirectWays=2 |
| 144instShiftAmt=2 145localCtrBits=2 146localHistoryTableSize=2048 147localPredictorSize=2048 148numThreads=1 |
| 149useIndirect=true |
| 150 151[system.cpu.dcache] 152type=Cache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain |
| 157clusivity=mostly_incl 158default_p_state=UNDEFINED |
| 159demand_mshr_reserve=1 160eventq_index=0 |
| 161hit_latency=2 162is_read_only=false 163max_miss_count=0 164mshrs=4 |
| 165p_state_clk_gate_bins=20 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null |
| 169prefetch_on_access=false 170prefetcher=Null 171response_latency=2 172sequential_access=false 173size=262144 174system=system 175tags=system.cpu.dcache.tags 176tgts_per_mshr=20 177write_buffers=8 |
| 178writeback_clean=false |
| 179cpu_side=system.cpu.dcache_port 180mem_side=system.cpu.toL2Bus.slave[1] 181 182[system.cpu.dcache.tags] 183type=LRU 184assoc=2 185block_size=64 186clk_domain=system.cpu_clk_domain |
| 187default_p_state=UNDEFINED |
| 188eventq_index=0 189hit_latency=2 |
| 190p_state_clk_gate_bins=20 191p_state_clk_gate_max=1000000000000 192p_state_clk_gate_min=1000 193power_model=Null |
| 194sequential_access=false 195size=262144 196 197[system.cpu.dstage2_mmu] 198type=ArmStage2MMU 199children=stage2_tlb 200eventq_index=0 201stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 208eventq_index=0 209is_stage2=true 210size=32 211walker=system.cpu.dstage2_mmu.stage2_tlb.walker 212 213[system.cpu.dstage2_mmu.stage2_tlb.walker] 214type=ArmTableWalker 215clk_domain=system.cpu_clk_domain |
| 216default_p_state=UNDEFINED |
| 217eventq_index=0 218is_stage2=true 219num_squash_per_cycle=2 |
| 220p_state_clk_gate_bins=20 221p_state_clk_gate_max=1000000000000 222p_state_clk_gate_min=1000 223power_model=Null |
| 224sys=system 225 226[system.cpu.dtb] 227type=ArmTLB 228children=walker 229eventq_index=0 230is_stage2=false 231size=64 232walker=system.cpu.dtb.walker 233 234[system.cpu.dtb.walker] 235type=ArmTableWalker 236clk_domain=system.cpu_clk_domain |
| 237default_p_state=UNDEFINED |
| 238eventq_index=0 239is_stage2=false 240num_squash_per_cycle=2 |
| 241p_state_clk_gate_bins=20 242p_state_clk_gate_max=1000000000000 243p_state_clk_gate_min=1000 244power_model=Null |
| 245sys=system 246port=system.cpu.toL2Bus.slave[3] 247 248[system.cpu.executeFuncUnits] 249type=MinorFUPool 250children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 251eventq_index=0 252funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 --- 376 unchanged lines hidden (view full) --- 629opClass=InstPrefetch 630 631[system.cpu.icache] 632type=Cache 633children=tags 634addr_ranges=0:18446744073709551615 635assoc=2 636clk_domain=system.cpu_clk_domain |
| 637clusivity=mostly_incl 638default_p_state=UNDEFINED |
| 639demand_mshr_reserve=1 640eventq_index=0 |
| 641hit_latency=2 642is_read_only=true 643max_miss_count=0 644mshrs=4 |
| 645p_state_clk_gate_bins=20 646p_state_clk_gate_max=1000000000000 647p_state_clk_gate_min=1000 648power_model=Null |
| 649prefetch_on_access=false 650prefetcher=Null 651response_latency=2 652sequential_access=false 653size=131072 654system=system 655tags=system.cpu.icache.tags 656tgts_per_mshr=20 657write_buffers=8 |
| 658writeback_clean=true |
| 659cpu_side=system.cpu.icache_port 660mem_side=system.cpu.toL2Bus.slave[0] 661 662[system.cpu.icache.tags] 663type=LRU 664assoc=2 665block_size=64 666clk_domain=system.cpu_clk_domain |
| 667default_p_state=UNDEFINED |
| 668eventq_index=0 669hit_latency=2 |
| 670p_state_clk_gate_bins=20 671p_state_clk_gate_max=1000000000000 672p_state_clk_gate_min=1000 673power_model=Null |
| 674sequential_access=false 675size=131072 676 677[system.cpu.interrupts] 678type=ArmInterrupts 679eventq_index=0 680 681[system.cpu.isa] 682type=ArmISA |
| 683decoderFlavour=Generic |
| 684eventq_index=0 685fpsid=1090793632 686id_aa64afr0_el1=0 687id_aa64afr1_el1=0 688id_aa64dfr0_el1=1052678 689id_aa64dfr1_el1=0 690id_aa64isar0_el1=0 691id_aa64isar1_el1=0 --- 31 unchanged lines hidden (view full) --- 723eventq_index=0 724is_stage2=true 725size=32 726walker=system.cpu.istage2_mmu.stage2_tlb.walker 727 728[system.cpu.istage2_mmu.stage2_tlb.walker] 729type=ArmTableWalker 730clk_domain=system.cpu_clk_domain |
| 731default_p_state=UNDEFINED |
| 732eventq_index=0 733is_stage2=true 734num_squash_per_cycle=2 |
| 735p_state_clk_gate_bins=20 736p_state_clk_gate_max=1000000000000 737p_state_clk_gate_min=1000 738power_model=Null |
| 739sys=system 740 741[system.cpu.itb] 742type=ArmTLB 743children=walker 744eventq_index=0 745is_stage2=false 746size=64 747walker=system.cpu.itb.walker 748 749[system.cpu.itb.walker] 750type=ArmTableWalker 751clk_domain=system.cpu_clk_domain |
| 752default_p_state=UNDEFINED |
| 753eventq_index=0 754is_stage2=false 755num_squash_per_cycle=2 |
| 756p_state_clk_gate_bins=20 757p_state_clk_gate_max=1000000000000 758p_state_clk_gate_min=1000 759power_model=Null |
| 760sys=system 761port=system.cpu.toL2Bus.slave[2] 762 763[system.cpu.l2cache] 764type=Cache 765children=tags 766addr_ranges=0:18446744073709551615 767assoc=8 768clk_domain=system.cpu_clk_domain |
| 769clusivity=mostly_incl 770default_p_state=UNDEFINED |
| 771demand_mshr_reserve=1 772eventq_index=0 |
| 773hit_latency=20 774is_read_only=false 775max_miss_count=0 776mshrs=20 |
| 777p_state_clk_gate_bins=20 778p_state_clk_gate_max=1000000000000 779p_state_clk_gate_min=1000 780power_model=Null |
| 781prefetch_on_access=false 782prefetcher=Null 783response_latency=20 784sequential_access=false 785size=2097152 786system=system 787tags=system.cpu.l2cache.tags 788tgts_per_mshr=12 789write_buffers=8 |
| 790writeback_clean=false |
| 791cpu_side=system.cpu.toL2Bus.master[0] 792mem_side=system.membus.slave[1] 793 794[system.cpu.l2cache.tags] 795type=LRU 796assoc=8 797block_size=64 798clk_domain=system.cpu_clk_domain |
| 799default_p_state=UNDEFINED |
| 800eventq_index=0 801hit_latency=20 |
| 802p_state_clk_gate_bins=20 803p_state_clk_gate_max=1000000000000 804p_state_clk_gate_min=1000 805power_model=Null |
| 806sequential_access=false 807size=2097152 808 809[system.cpu.toL2Bus] 810type=CoherentXBar |
| 811children=snoop_filter |
| 812clk_domain=system.cpu_clk_domain |
| 813default_p_state=UNDEFINED |
| 814eventq_index=0 815forward_latency=0 816frontend_latency=1 |
| 817p_state_clk_gate_bins=20 818p_state_clk_gate_max=1000000000000 819p_state_clk_gate_min=1000 820point_of_coherency=false 821power_model=Null |
| 822response_latency=1 |
| 823snoop_filter=system.cpu.toL2Bus.snoop_filter |
| 824snoop_response_latency=1 825system=system 826use_default_range=false 827width=32 828master=system.cpu.l2cache.cpu_side 829slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 830 |
| 831[system.cpu.toL2Bus.snoop_filter] 832type=SnoopFilter 833eventq_index=0 834lookup_latency=0 835max_capacity=8388608 836system=system 837 |
| 838[system.cpu.tracer] 839type=ExeTracer 840eventq_index=0 841 842[system.cpu.workload] 843type=LiveProcess 844cmd=twolf smred 845cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing 846drivers= 847egid=100 848env= 849errout=cerr 850euid=100 851eventq_index=0 |
| 852executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf |
| 853gid=100 854input=cin 855kvmInSE=false 856max_stack_size=67108864 857output=cout 858pid=100 859ppid=99 860simpoint=0 --- 15 unchanged lines hidden (view full) --- 876enable=false 877eventq_index=0 878sys_clk_domain=system.clk_domain 879transition_latency=100000000 880 881[system.membus] 882type=CoherentXBar 883clk_domain=system.clk_domain |
| 884default_p_state=UNDEFINED |
| 885eventq_index=0 886forward_latency=4 887frontend_latency=3 |
| 888p_state_clk_gate_bins=20 889p_state_clk_gate_max=1000000000000 890p_state_clk_gate_min=1000 891point_of_coherency=true 892power_model=Null |
| 893response_latency=2 894snoop_filter=Null 895snoop_response_latency=4 896system=system 897use_default_range=false 898width=16 899master=system.physmem.port 900slave=system.system_port system.cpu.l2cache.mem_side --- 27 unchanged lines hidden (view full) --- 928activation_limit=4 929addr_mapping=RoRaBaCoCh 930bank_groups_per_rank=0 931banks_per_rank=8 932burst_length=8 933channels=1 934clk_domain=system.clk_domain 935conf_table_reported=true |
| 936default_p_state=UNDEFINED |
| 937device_bus_width=8 938device_rowbuffer_size=1024 939device_size=536870912 940devices_per_rank=8 941dll=true 942eventq_index=0 943in_addr_map=true 944max_accesses_per_row=16 945mem_sched_policy=frfcfs 946min_writes_per_switch=16 947null=false |
| 948p_state_clk_gate_bins=20 949p_state_clk_gate_max=1000000000000 950p_state_clk_gate_min=1000 |
| 951page_policy=open_adaptive |
| 952power_model=Null |
| 953range=0:134217727 954ranks_per_channel=2 955read_buffer_size=32 956static_backend_latency=10000 957static_frontend_latency=10000 958tBURST=5000 959tCCD_L=0 960tCK=1250 --- 28 unchanged lines hidden --- |