| stats.txt (9702:094d0280e481) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882581 # Number of seconds simulated 4sim_ticks 5882580526000 # Number of ticks simulated 5final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 548624 # Simulator instruction rate (inst/s) 8host_op_rate 854806 # Simulator op (including micro ops) rate (op/s) --- 20 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882581 # Number of seconds simulated 4sim_ticks 5882580526000 # Number of ticks simulated 5final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 548624 # Simulator instruction rate (inst/s) 8host_op_rate 854806 # Simulator op (including micro ops) rate (op/s) --- 20 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) |
| 37system.membus.throughput 32392097 # Throughput (bytes/s) 38system.membus.trans_dist::ReadReq 1177614 # Transaction distribution 39system.membus.trans_dist::ReadResp 1177614 # Transaction distribution 40system.membus.trans_dist::Writeback 1018421 # Transaction distribution 41system.membus.trans_dist::ReadExReq 781295 # Transaction distribution 42system.membus.trans_dist::ReadExResp 781295 # Transaction distribution 43system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) 44system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 190549120 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 53system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 55system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.3 # Layer utilization (%) |
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| 37system.cpu.workload.num_syscalls 46 # Number of system calls 38system.cpu.numCycles 11765161052 # number of cpu cycles simulated 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 3008081022 # Number of instructions committed 42system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses 44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 320 unchanged lines hidden (view full) --- 365system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency 366system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency 367system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency 368system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 369system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 370system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 371system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 372system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 57system.cpu.workload.num_syscalls 46 # Number of system calls 58system.cpu.numCycles 11765161052 # number of cpu cycles simulated 59system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 60system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 61system.cpu.committedInsts 3008081022 # Number of instructions committed 62system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 63system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses 64system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 320 unchanged lines hidden (view full) --- 385system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency 386system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency 387system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency 388system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 389system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 390system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 391system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 392system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 393system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s) 394system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution 395system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 396system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution 397system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 398system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 399system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes) 400system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes) 401system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes) 402system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes) 403system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes) 404system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes) 405system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) 406system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 407system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) 408system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 409system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 410system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 411system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 412system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
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| 373 374---------- End Simulation Statistics ---------- | 413 414---------- End Simulation Statistics ---------- |