| stats.txt (9322:01c8c5ff2c3b) | stats.txt (9373:26ba525347fe) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882581 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882581 # Number of seconds simulated |
| 4sim_ticks 5882580524000 # Number of ticks simulated 5final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 5882580525000 # Number of ticks simulated 5final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 472403 # Simulator instruction rate (inst/s) 8host_op_rate 736047 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 923827707 # Simulator tick rate (ticks/s) 10host_mem_usage 227772 # Number of bytes of host memory used 11host_seconds 6367.62 # Real time elapsed on the host | 7host_inst_rate 506721 # Simulator instruction rate (inst/s) 8host_op_rate 789517 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 990939541 # Simulator tick rate (ticks/s) 10host_mem_usage 276172 # Number of bytes of host memory used 11host_seconds 5936.37 # Real time elapsed on the host |
| 12sim_insts 3008081022 # Number of instructions simulated | 12sim_insts 3008081022 # Number of instructions simulated |
| 13sim_ops 4686862594 # Number of ops (including micro ops) simulated | 13sim_ops 4686862595 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory 16system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory 20system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 46 # Number of system calls | 14system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory 16system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory 20system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory --- 8 unchanged lines hidden (view full) --- 30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.workload.num_syscalls 46 # Number of system calls |
| 38system.cpu.numCycles 11765161048 # number of cpu cycles simulated | 38system.cpu.numCycles 11765161050 # number of cpu cycles simulated |
| 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 3008081022 # Number of instructions committed | 39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41system.cpu.committedInsts 3008081022 # Number of instructions committed |
| 42system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses | 42system.cpu.committedOps 4686862595 # Number of ops (including micro ops) committed 43system.cpu.num_int_alu_accesses 4686862525 # Number of integer alu accesses |
| 44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls | 44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 45system.cpu.num_func_calls 0 # number of times a function call or return occured 46system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls |
| 47system.cpu.num_int_insts 4686862523 # number of integer instructions | 47system.cpu.num_int_insts 4686862525 # number of integer instructions |
| 48system.cpu.num_fp_insts 0 # number of float instructions | 48system.cpu.num_fp_insts 0 # number of float instructions |
| 49system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read 50system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written | 49system.cpu.num_int_register_reads 11915474423 # number of times the integer registers were read 50system.cpu.num_int_register_writes 5355771936 # number of times the integer registers were written |
| 51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 53system.cpu.num_mem_refs 1677713082 # number of memory refs | 53system.cpu.num_mem_refs 1677713083 # number of memory refs |
| 54system.cpu.num_load_insts 1239184745 # Number of load instructions | 54system.cpu.num_load_insts 1239184745 # Number of load instructions |
| 55system.cpu.num_store_insts 438528337 # Number of store instructions | 55system.cpu.num_store_insts 438528338 # Number of store instructions |
| 56system.cpu.num_idle_cycles 0 # Number of idle cycles | 56system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 57system.cpu.num_busy_cycles 11765161048 # Number of busy cycles | 57system.cpu.num_busy_cycles 11765161050 # Number of busy cycles |
| 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 10 # number of replacements 61system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use 62system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. --- 66 unchanged lines hidden (view full) --- 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 9108581 # number of replacements 139system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use | 58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 59system.cpu.idle_fraction 0 # Percentage of idle cycles 60system.cpu.icache.replacements 10 # number of replacements 61system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use 62system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. 63system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. 64system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. 65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. --- 66 unchanged lines hidden (view full) --- 132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency 133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 134system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 136system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 138system.cpu.dcache.replacements 9108581 # number of replacements 139system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use |
| 140system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. | 140system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks. |
| 141system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. | 141system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. 142system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. |
| 143system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit. | 143system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit. |
| 144system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor 145system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits | 144system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor 145system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 146system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy 147system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits 148system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits |
| 149system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits 154system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits | 149system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 150system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 151system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits 152system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits 153system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits 154system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits |
| 155system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 162system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) | 155system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 156system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 157system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 158system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 159system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 160system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 161system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 162system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 163system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles 164system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles 165system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles 166system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles 167system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles 168system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles 169system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles 170system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles 171system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) 172system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) |
| 173system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses | 173system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 174system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 175system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses 176system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses 177system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses 178system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses |
| 179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses --- 44 unchanged lines hidden (view full) --- 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 1926197 # number of replacements | 179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 180system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 182system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 183system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 184system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 185system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 186system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses --- 44 unchanged lines hidden (view full) --- 231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency 232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency 233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 234system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 236system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 238system.cpu.l2cache.replacements 1926197 # number of replacements |
| 239system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use | 239system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use |
| 240system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. | 240system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. 241system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. 242system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. |
| 243system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit. 244system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor | 243system.cpu.l2cache.warmup_cycle 340768634000 # Cycle when the warmup percentage was hit. 244system.cpu.l2cache.occ_blocks::writebacks 15396.795536 # Average occupied blocks per requestor |
| 245system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor | 245system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor |
| 246system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor | 246system.cpu.l2cache.occ_blocks::cpu.data 15713.812833 # Average occupied blocks per requestor |
| 247system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy 248system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy 249system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy 250system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy 251system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits 252system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits 253system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits 254system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits --- 120 unchanged lines hidden --- | 247system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy 248system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy 249system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy 250system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy 251system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits 252system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits 253system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits 254system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits --- 120 unchanged lines hidden --- |