Cross Reference: /gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 5.891582 # Number of seconds simulated
4sim_ticks 5891581948000 # Number of ticks simulated
5final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 5.882581 # Number of seconds simulated
4sim_ticks 5882580524000 # Number of ticks simulated
5final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 701685 # Simulator instruction rate (inst/s)
8host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1374310212 # Simulator tick rate (ticks/s)
10host_mem_usage 228764 # Number of bytes of host memory used
11host_seconds 4286.94 # Real time elapsed on the host

7host_inst_rate 472403 # Simulator instruction rate (inst/s)
8host_op_rate 736047 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 923827707 # Simulator tick rate (ticks/s)
10host_mem_usage 227772 # Number of bytes of host memory used
11host_seconds 6367.62 # Real time elapsed on the host

12sim_insts 3008081022 # Number of instructions simulated
13sim_ops 4686862594 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
16system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
16system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory

17system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory

19system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
20system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory

19system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory
20system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory

21system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory

22system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s)

22system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)

37system.cpu.workload.num_syscalls 46 # Number of system calls

38system.cpu.numCycles 11783163896 # number of cpu cycles simulated

38system.cpu.numCycles 11765161048 # number of cpu cycles simulated

39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41system.cpu.committedInsts 3008081022 # Number of instructions committed
42system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
43system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45system.cpu.num_func_calls 0 # number of times a function call or return occured
46system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
47system.cpu.num_int_insts 4686862523 # number of integer instructions
48system.cpu.num_fp_insts 0 # number of float instructions
49system.cpu.num_int_register_reads 11915474418 # number of times the integer registers were read
50system.cpu.num_int_register_writes 5355771935 # number of times the integer registers were written
51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53system.cpu.num_mem_refs 1677713082 # number of memory refs
54system.cpu.num_load_insts 1239184745 # Number of load instructions
55system.cpu.num_store_insts 438528337 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles

57system.cpu.num_busy_cycles 11783163896 # Number of busy cycles

57system.cpu.num_busy_cycles 11765161048 # Number of busy cycles

58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59system.cpu.idle_fraction 0 # Percentage of idle cycles
60system.cpu.icache.replacements 10 # number of replacements

61system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use

61system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use

62system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
63system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
64system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

66system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor
67system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy

66system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
67system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy

69system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
70system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
71system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
72system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
73system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
74system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
75system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
76system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
77system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
78system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
79system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
80system.cpu.icache.overall_misses::total 675 # number of overall misses

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles

87system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
88system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
89system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
90system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
91system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
92system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
94system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
96system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
98system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency

105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111system.cpu.icache.fast_writes 0 # number of fast writes performed
112system.cpu.icache.cache_copies 0 # number of cache copies performed
113system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
114system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
115system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
116system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
117system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
118system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles

125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
128system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
130system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency

137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138system.cpu.dcache.replacements 9108581 # number of replacements

139system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use

139system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use

140system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
141system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
142system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.

143system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit.
144system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy

143system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit.
144system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
145system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy

147system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
148system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
150system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
151system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
152system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
153system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
154system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
155system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
156system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
157system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
158system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
159system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
160system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
161system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
162system.cpu.dcache.overall_misses::total 9112677 # number of overall misses

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles

171system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
174system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
175system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
176system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
177system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
178system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
183system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
184system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
185system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
186system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency

195system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
199system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
200system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
201system.cpu.dcache.fast_writes 0 # number of fast writes performed
202system.cpu.dcache.cache_copies 0 # number of cache copies performed

203system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks
204system.cpu.dcache.writebacks::total 3375759 # number of writebacks

203system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
204system.cpu.dcache.writebacks::total 3697956 # number of writebacks

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206system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
207system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
208system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
209system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
210system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
211system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
212system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles

221system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
222system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
223system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
224system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
225system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
226system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
227system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
228system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency

237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

238system.cpu.l2cache.replacements 2158210 # number of replacements
239system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks.
243system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits
253system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits
254system.cpu.l2cache.Writeback_hits::total 3375759 # number of Writeback hits
255system.cpu.l2cache.ReadExReq_hits::cpu.data 1099986 # number of ReadExReq hits
256system.cpu.l2cache.ReadExReq_hits::total 1099986 # number of ReadExReq hits
257system.cpu.l2cache.demand_hits::cpu.data 6940121 # number of demand (read+write) hits
258system.cpu.l2cache.demand_hits::total 6940121 # number of demand (read+write) hits
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260system.cpu.l2cache.overall_hits::total 6940121 # number of overall hits

238system.cpu.l2cache.replacements 1926197 # number of replacements
239system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use
240system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks.
243system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
248system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
249system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy
251system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
252system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
253system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
254system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits
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256system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits
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265system.cpu.l2cache.ReadExReq_misses::total 789841 # number of ReadExReq misses

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265system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses

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267system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses
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269system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses

270system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses
271system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses
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277system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles
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281system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles
282system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles

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281system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles
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286system.cpu.l2cache.Writeback_accesses::writebacks 3375759 # number of Writeback accesses(hits+misses)
287system.cpu.l2cache.Writeback_accesses::total 3375759 # number of Writeback accesses(hits+misses)

286system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses)
287system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses)

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291system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
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294system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
295system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
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297system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.191436 # miss rate for ReadReq accesses
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300system.cpu.l2cache.ReadExReq_miss_rate::total 0.417944 # miss rate for ReadExReq accesses

297system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses
298system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses
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300system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses

301system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses

302system.cpu.l2cache.demand_miss_rate::cpu.data 0.238410 # miss rate for demand accesses
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304system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses

305system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses
306system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses
307system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency
308system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency
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310system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency
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312system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency
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315system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency
316system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency
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305system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses
306system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses
307system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency
308system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency
309system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency
310system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency
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312system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
313system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
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315system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
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318system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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323system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
324system.cpu.l2cache.fast_writes 0 # number of fast writes performed
325system.cpu.l2cache.cache_copies 0 # number of cache copies performed

326system.cpu.l2cache.writebacks::writebacks 1053029 # number of writebacks
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326system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks
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348system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles
349system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles

350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses

351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses
352system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses
353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses
354system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses

351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses
352system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses
353system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses
354system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses

355system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses

356system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses
357system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses

356system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses
357system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses

358system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses

359system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses
360system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses
361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency
362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency
363system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency
364system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency
365system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency
366system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
367system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
368system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency
369system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency
370system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency
371system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency

359system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses
360system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses
361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency
362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency
363system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency
364system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency
365system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency
366system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
367system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
368system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
369system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
370system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
371system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency