Cross Reference: /gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 5.900695 # Number of seconds simulated
4sim_ticks 5900695290000 # Number of ticks simulated
5final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 5.901049 # Number of seconds simulated
4sim_ticks 5901048931000 # Number of ticks simulated
5final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1070782 # Simulator instruction rate (inst/s)
8host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2100461088 # Simulator tick rate (ticks/s)
10host_mem_usage 228516 # Number of bytes of host memory used
11host_seconds 2809.24 # Real time elapsed on the host

7host_inst_rate 821481 # Simulator instruction rate (inst/s)
8host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1611526350 # Simulator tick rate (ticks/s)
10host_mem_usage 228472 # Number of bytes of host memory used
11host_seconds 3661.78 # Real time elapsed on the host

12sim_insts 3008081057 # Number of instructions simulated
13sim_ops 4686862651 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
16system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory
20system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 7321 # Total read bandwidth from this memory (bytes/s)

27system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s)

27system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_inst_read::cpu.inst 7321 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 7321 # Instruction read bandwidth from this memory (bytes/s)

31system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s)

31system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s)

34system.physmem.bw_total::cpu.inst 7321 # Total bandwidth to/from this memory (bytes/s)

35system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s)

35system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s)

37system.cpu.workload.num_syscalls 46 # Number of system calls

38system.cpu.numCycles 11801390580 # number of cpu cycles simulated

38system.cpu.numCycles 11802097862 # number of cpu cycles simulated

39system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
40system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
41system.cpu.committedInsts 3008081057 # Number of instructions committed
42system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
43system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
44system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
45system.cpu.num_func_calls 0 # number of times a function call or return occured
46system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
47system.cpu.num_int_insts 4686862580 # number of integer instructions
48system.cpu.num_fp_insts 0 # number of float instructions
49system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
50system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
51system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
52system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
53system.cpu.num_mem_refs 1677713086 # number of memory refs
54system.cpu.num_load_insts 1239184749 # Number of load instructions
55system.cpu.num_store_insts 438528337 # Number of store instructions
56system.cpu.num_idle_cycles 0 # Number of idle cycles

57system.cpu.num_busy_cycles 11801390580 # Number of busy cycles

57system.cpu.num_busy_cycles 11802097862 # Number of busy cycles

58system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
59system.cpu.idle_fraction 0 # Percentage of idle cycles
60system.cpu.icache.replacements 10 # number of replacements

61system.cpu.icache.tagsinuse 555.745205 # Cycle average of tags in use

61system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use

62system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
63system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
64system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
65system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

66system.cpu.icache.occ_blocks::cpu.inst 555.745205 # Average occupied blocks per requestor

66system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor

67system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy
68system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy
69system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
70system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
71system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
72system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits
73system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits
74system.cpu.icache.overall_hits::total 4013232252 # number of overall hits
75system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
76system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
77system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
78system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
79system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
80system.cpu.icache.overall_misses::total 675 # number of overall misses

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles

81system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles
82system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles
83system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles
84system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles
85system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles
86system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles

87system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses)
88system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses)
89system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses
90system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses
91system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses
92system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses
93system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
94system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
95system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
96system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
97system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
98system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency

99system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency
100system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
102system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency
103system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
104system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency

105system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
106system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
107system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
108system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
109system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
110system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
111system.cpu.icache.fast_writes 0 # number of fast writes performed
112system.cpu.icache.cache_copies 0 # number of cache copies performed
113system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
114system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
115system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
116system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
117system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
118system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles

119system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles
120system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles
121system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles
122system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles
123system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles
124system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles

125system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
126system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
127system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
128system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
130system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency

131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency
132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency
133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
134system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
136system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency

137system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
138system.cpu.dcache.replacements 9108581 # number of replacements

139system.cpu.dcache.tagsinuse 4084.618409 # Cycle average of tags in use

139system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use

140system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
141system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
142system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.

143system.cpu.dcache.warmup_cycle 58862653000 # Cycle when the warmup percentage was hit.
144system.cpu.dcache.occ_blocks::cpu.data 4084.618409 # Average occupied blocks per requestor

143system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit.
144system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor

145system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy
146system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy
147system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits
148system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits
149system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
150system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
151system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits
152system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits
153system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits
154system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits
155system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
156system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
157system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
158system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
159system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
160system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
161system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
162system.cpu.dcache.overall_misses::total 9112677 # number of overall misses

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 159193930000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 59630900000 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 59630900000 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 218824830000 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 218824830000 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 218824830000 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 218824830000 # number of overall miss cycles

163system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles
164system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles
165system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles
166system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles
167system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles
168system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles
169system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles
170system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles

171system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses)
172system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses)
173system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
174system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
175system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses
176system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses
177system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses
178system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses
179system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
180system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
181system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
182system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
183system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
184system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
185system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
186system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 24013.232336 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 24013.232336 # average overall miss latency

187system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency
188system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency
189system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
192system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency
193system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
194system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency

195system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
196system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
197system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
198system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
199system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
200system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
201system.cpu.dcache.fast_writes 0 # number of fast writes performed
202system.cpu.dcache.cache_copies 0 # number of cache copies performed
203system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks
204system.cpu.dcache.writebacks::total 3375759 # number of writebacks
205system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
206system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
207system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
208system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
209system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
210system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
211system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
212system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961419000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961419000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 191486799000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 191486799000 # number of overall MSHR miss cycles

213system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles
214system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles
215system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles
216system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles
217system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles
218system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles
219system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles
220system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles

221system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
222system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
223system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
224system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
225system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
226system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
227system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
228system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency

229system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency
230system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency
231system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency
232system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency
233system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
234system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
235system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
236system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency

237system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
238system.cpu.l2cache.replacements 2158210 # number of replacements

239system.cpu.l2cache.tagsinuse 30851.506102 # Cycle average of tags in use

239system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use

240system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks.
241system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks.
242system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks.

243system.cpu.l2cache.warmup_cycle 1317336331000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 14661.525978 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 21.582601 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 16168.397523 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.447434 # Average percentage of cache occupancy

243system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit.
244system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor
245system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor
246system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor
247system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy

248system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy

249system.cpu.l2cache.occ_percent::cpu.data 0.493420 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.941513 # Average percentage of cache occupancy

249system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy
250system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy