| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.923548 # Number of seconds simulated 4sim_ticks 5923548078000 # Number of ticks simulated 5final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.923548 # Number of seconds simulated 4sim_ticks 5923548078000 # Number of ticks simulated 5final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1064786 # Simulator instruction rate (inst/s) 8host_op_rate 1659033 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2096788716 # Simulator tick rate (ticks/s) 10host_mem_usage 219100 # Number of bytes of host memory used 11host_seconds 2825.06 # Real time elapsed on the host | 7host_inst_rate 443317 # Simulator instruction rate (inst/s) 8host_op_rate 690728 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 872984671 # Simulator tick rate (ticks/s) 10host_mem_usage 224336 # Number of bytes of host memory used 11host_seconds 6785.40 # Real time elapsed on the host |
| 12sim_insts 3008081057 # Number of instructions simulated 13sim_ops 4686862651 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 173910080 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 75176384 # Number of bytes written to this memory 17system.physmem.num_reads 2717345 # Number of read requests responded to by this memory 18system.physmem.num_writes 1174631 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 62 unchanged lines hidden (view full) --- 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 3008081057 # Number of instructions simulated 13sim_ops 4686862651 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 173910080 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 75176384 # Number of bytes written to this memory 17system.physmem.num_reads 2717345 # Number of read requests responded to by this memory 18system.physmem.num_writes 1174631 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 62 unchanged lines hidden (view full) --- 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 90system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 90system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses --- 58 unchanged lines hidden (view full) --- 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency 159system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency 160system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency 161system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency 162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses --- 58 unchanged lines hidden (view full) --- 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171 # average ReadReq miss latency 159system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483 # average WriteReq miss latency 160system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency 161system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159 # average overall miss latency 162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 166system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 167system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 166system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 167system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 168system.cpu.dcache.fast_writes 0 # number of fast writes performed 169system.cpu.dcache.cache_copies 0 # number of cache copies performed 170system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks 171system.cpu.dcache.writebacks::total 3053391 # number of writebacks 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses --- 89 unchanged lines hidden (view full) --- 265system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 266system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 267system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 268system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 269system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 270system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 271system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 272system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 168system.cpu.dcache.fast_writes 0 # number of fast writes performed 169system.cpu.dcache.cache_copies 0 # number of cache copies performed 170system.cpu.dcache.writebacks::writebacks 3053391 # number of writebacks 171system.cpu.dcache.writebacks::total 3053391 # number of writebacks 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses --- 89 unchanged lines hidden (view full) --- 265system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 266system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 267system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 268system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 269system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 270system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 271system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 272system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 273system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 274system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 273system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 274system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 275system.cpu.l2cache.fast_writes 0 # number of fast writes performed 276system.cpu.l2cache.cache_copies 0 # number of cache copies performed 277system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks 278system.cpu.l2cache.writebacks::total 1174631 # number of writebacks 279system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 280system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses 281system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses 282system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses --- 35 unchanged lines hidden --- | 275system.cpu.l2cache.fast_writes 0 # number of fast writes performed 276system.cpu.l2cache.cache_copies 0 # number of cache copies performed 277system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks 278system.cpu.l2cache.writebacks::total 1174631 # number of writebacks 279system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 280system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses 281system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses 282system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses --- 35 unchanged lines hidden --- |