Cross Reference: /gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 5.895948 # Number of seconds simulated
4sim_ticks 5895947852500 # Number of ticks simulated
5final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 5.898831 # Number of seconds simulated
4sim_ticks 5898831348500 # Number of ticks simulated
5final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 735742 # Simulator instruction rate (inst/s)
8host_op_rate 1146353 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1442081312 # Simulator tick rate (ticks/s)
10host_mem_usage 269296 # Number of bytes of host memory used
11host_seconds 4088.50 # Real time elapsed on the host

7host_inst_rate 637466 # Simulator instruction rate (inst/s)
8host_op_rate 993229 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1250066735 # Simulator tick rate (ticks/s)
10host_mem_usage 275724 # Number of bytes of host memory used
11host_seconds 4718.81 # Real time elapsed on the host

12sim_insts 3008081022 # Number of instructions simulated
13sim_ops 4686862596 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
19system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory
19system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory

20system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory

22system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
23system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory

22system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory
23system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory

24system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory

25system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

25system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

41system.cpu_clk_domain.clock 500 # Clock period in ticks

42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks

44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

46system.cpu.workload.num_syscalls 46 # Number of system calls

47system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
48system.cpu.numCycles 11791895705 # number of cpu cycles simulated

47system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states
48system.cpu.numCycles 11797662697 # number of cpu cycles simulated

49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
51system.cpu.committedInsts 3008081022 # Number of instructions committed
52system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
53system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
55system.cpu.num_func_calls 33534539 # number of times a function call or return occured
56system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

61system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
62system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
63system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
64system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
65system.cpu.num_mem_refs 1677713084 # number of memory refs
66system.cpu.num_load_insts 1239184746 # Number of load instructions
67system.cpu.num_store_insts 438528338 # Number of store instructions
68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

69system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles

69system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles

70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
72system.cpu.Branches 248500691 # Number of branches fetched
73system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
74system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
75system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
76system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
77system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

100system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
101system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
102system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
103system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
104system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
105system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
106system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
107system.cpu.op_class::total 4686862596 # Class of executed instruction

108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

109system.cpu.dcache.tags.replacements 9108581 # number of replacements

110system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use

110system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use

111system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
112system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
113system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.

114system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
115system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor

114system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit.
115system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor

116system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
117system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
118system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id

119system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
120system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
121system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id

119system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
120system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id
121system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id

122system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
123system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
124system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
125system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
126system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses

127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

128system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
129system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
130system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
131system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
132system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
133system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
134system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
135system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
136system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
137system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
138system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
139system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
140system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
141system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
142system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
143system.cpu.dcache.overall_misses::total 9112677 # number of overall misses

144system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
145system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
146system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
147system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
148system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
149system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
150system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
151system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles

144system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles
145system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles
146system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles
147system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles
148system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles
149system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles
150system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles
151system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles

152system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
153system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
154system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
155system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
156system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
157system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
158system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
159system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
160system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
161system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
162system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
163system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
164system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
165system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
166system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
167system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses

168system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
169system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
170system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
171system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
172system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
173system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
174system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
175system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency

168system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency
169system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency
170system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency
171system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency
172system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
173system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency
174system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
175system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency

176system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
177system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
178system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
179system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
180system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
181system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

182system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
183system.cpu.dcache.writebacks::total 3682716 # number of writebacks

182system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks
183system.cpu.dcache.writebacks::total 3669049 # number of writebacks

184system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
185system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
186system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
187system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
188system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
189system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
190system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
191system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses

192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
193system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
196system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
197system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
198system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
199system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles

192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles
193system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles
194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles
195system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles
196system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles
197system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles
198system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles
199system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles

200system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
201system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
202system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
203system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
204system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
205system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
207system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses

208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency
212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

217system.cpu.icache.tags.replacements 10 # number of replacements

218system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use

218system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use

219system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
220system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
221system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

223system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
224system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
225system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy

223system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor
224system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy
225system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy

226system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
227system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
228system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
229system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
230system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
231system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses

232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

233system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
234system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
235system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
236system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
237system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
238system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
239system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
240system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
241system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
242system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
243system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
244system.cpu.icache.overall_misses::total 675 # number of overall misses

245system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
246system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
247system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
248system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
249system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
250system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles

245system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles
246system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles
247system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles
248system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles
249system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles
250system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles

251system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
252system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
253system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
254system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses
255system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses
256system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses
257system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
258system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
259system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
260system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
261system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
262system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses

263system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
264system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
265system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
266system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
267system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
268system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency

263system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency
264system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency
265system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
266system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency
267system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
268system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency

269system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
270system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
271system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
272system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
273system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
274system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
275system.cpu.icache.writebacks::writebacks 10 # number of writebacks
276system.cpu.icache.writebacks::total 10 # number of writebacks
277system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
278system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
279system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
280system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
281system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
282system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses

283system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
284system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
285system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
286system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
287system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
288system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles

283system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles
284system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles
285system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles
286system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles
287system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles
288system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles

289system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
290system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
291system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
292system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
294system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses

295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
298system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
300system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
302system.cpu.l2cache.tags.replacements 1919169 # number of replacements
303system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
304system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
305system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
306system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
307system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
308system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
310system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
311system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
312system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
313system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
314system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
315system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
322system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
323system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
324system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
325system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
326system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits

295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency
296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency
297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
298system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
300system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
302system.cpu.l2cache.tags.replacements 1938075 # number of replacements
303system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use
304system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks.
305system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks.
306system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks.
307system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit.
308system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor
310system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor
311system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy
312system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy
313system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy
314system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy
315system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id
318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id
321system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
322system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses
323system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses
324system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
325system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits
326system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits

327system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
328system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits

329system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
330system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
331system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
332system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
333system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
334system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
335system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
336system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
337system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
338system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses

329system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits
330system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits
331system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits
332system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits
333system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits
334system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits
335system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits
336system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits
337system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses
338system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses

339system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses
340system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses

341system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
342system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses

341system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses
342system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses

343system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses

344system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
345system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses

344system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses
345system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses

346system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses

347system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
348system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
349system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
350system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
351system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
352system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
353system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
354system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
355system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
356system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
357system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
358system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
359system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
360system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
361system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
362system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)

347system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses
348system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses
349system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles
350system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles
351system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles
352system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles
353system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles
354system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles
355system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles
356system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles
357system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles
358system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles
359system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles
360system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles
361system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses)
362system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses)

363system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
364system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
365system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
366system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
367system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses)
368system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses)
369system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses)
370system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses)
371system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
372system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
373system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
374system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
375system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
376system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses

377system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses
378system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses

377system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses
378system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses

379system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
380system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses

381system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
382system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses

381system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses
382system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses

383system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses

384system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
385system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses

384system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses
385system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses

386system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses

387system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
388system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
389system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
390system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
391system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
392system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
393system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
394system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
395system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
396system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
397system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
398system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
399system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
400system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency

387system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses
388system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses
389system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
390system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
391system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency
392system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency
393system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency
394system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency
395system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
396system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
397system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency
398system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
399system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
400system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency

401system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
402system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
403system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
404system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
405system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
406system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

407system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
408system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
409system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
410system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
411system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
412system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses

407system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks
408system.cpu.l2cache.writebacks::total 1032938 # number of writebacks
409system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses
410system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses
411system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses
412system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses

413system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses
414system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses

415system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
416system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses

415system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses
416system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses

417system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses

418system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
419system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses

418system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses
419system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses

420system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses

421system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
422system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
423system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
424system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
425system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
426system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
427system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
428system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
429system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
430system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
431system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
432system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
433system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
434system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles

421system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses
422system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses
423system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles
424system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles
425system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles
426system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles
427system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles
428system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles
429system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles
430system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles
431system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles
432system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles
433system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles
434system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles

435system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
436system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

437system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
438system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses

437system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses
438system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses

439system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
440system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses

441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
442system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses

441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses
442system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses

443system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses

444system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
445system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses

444system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses
445system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses

446system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses

447system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
448system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
450system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
452system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
454system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
456system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
457system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
460system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency

447system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses
448system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses
449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
450system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency
452system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency
453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency
454system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency
455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
456system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
457system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
460system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency

461system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
462system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

464system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

464system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

467system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states

467system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states

468system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution

469system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution

469system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution

470system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution

471system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution

471system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution

472system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
473system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
474system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
475system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution
476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes)
477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes)
478system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes)
479system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes)

480system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
481system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
482system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
483system.cpu.toL2Bus.snoopTraffic 65426496 # Total snoop traffic (bytes)
484system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram

480system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes)
481system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes)
482system.cpu.toL2Bus.snoops 1938075 # Total snoops (count)
483system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes)
484system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram
486system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram

487system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

488system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
489system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram

488system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram
489system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram

490system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
491system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
492system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
493system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

494system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
495system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)

494system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram
495system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks)

496system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
497system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
498system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
499system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
500system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)

501system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
502system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
503system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
504system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
505system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
506system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
507system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
509system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
510system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
511system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
512system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
513system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)

501system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter.
502system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data.
503system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
504system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
505system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
506system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
507system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
508system.membus.trans_dist::ReadResp 1176539 # Transaction distribution
509system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution
510system.membus.trans_dist::CleanEvict 904164 # Transaction distribution
511system.membus.trans_dist::ReadExReq 793964 # Transaction distribution
512system.membus.trans_dist::ReadExResp 793964 # Transaction distribution
513system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution
514system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes)
515system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes)
516system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes)
517system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes)
518system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes)
519system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes)

514system.membus.snoops 0 # Total snoops (count)
515system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

520system.membus.snoops 0 # Total snoops (count)
521system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

516system.membus.snoop_fanout::samples 3870249 # Request fanout histogram

522system.membus.snoop_fanout::samples 1970503 # Request fanout histogram

517system.membus.snoop_fanout::mean 0 # Request fanout histogram
518system.membus.snoop_fanout::stdev 0 # Request fanout histogram
519system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

523system.membus.snoop_fanout::mean 0 # Request fanout histogram
524system.membus.snoop_fanout::stdev 0 # Request fanout histogram
525system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

520system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram

526system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram

521system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
522system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
523system.membus.snoop_fanout::min_value 0 # Request fanout histogram
524system.membus.snoop_fanout::max_value 0 # Request fanout histogram

527system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
528system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
529system.membus.snoop_fanout::min_value 0 # Request fanout histogram
530system.membus.snoop_fanout::max_value 0 # Request fanout histogram

525system.membus.snoop_fanout::total 3870249 # Request fanout histogram
526system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)

531system.membus.snoop_fanout::total 1970503 # Request fanout histogram
532system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks)

527system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

533system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)

528system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)

534system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks)