| stats.txt (10488:7c27480a5031) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.882581 # Number of seconds simulated 4sim_ticks 5882580526000 # Number of ticks simulated 5final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.882580 # Number of seconds simulated 4sim_ticks 5882580398500 # Number of ticks simulated 5final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 912016 # Simulator instruction rate (inst/s) 8host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1783532526 # Simulator tick rate (ticks/s) 10host_mem_usage 308940 # Number of bytes of host memory used 11host_seconds 3298.27 # Real time elapsed on the host | 7host_inst_rate 733187 # Simulator instruction rate (inst/s) 8host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1433815394 # Simulator tick rate (ticks/s) 10host_mem_usage 313792 # Number of bytes of host memory used 11host_seconds 4102.75 # Real time elapsed on the host |
| 12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) | 12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) |
| 30system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s) | 30system.physmem.bw_read::total 21312106 # Total read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) | 31system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) |
| 38system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) 39system.membus.trans_dist::ReadReq 1177614 # Transaction distribution 40system.membus.trans_dist::ReadResp 1177614 # Transaction distribution 41system.membus.trans_dist::Writeback 1018421 # Transaction distribution 42system.membus.trans_dist::ReadExReq 781295 # Transaction distribution 43system.membus.trans_dist::ReadExResp 781295 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) 47system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) 50system.membus.snoops 0 # Total snoops (count) 51system.membus.snoop_fanout::samples 2977330 # Request fanout histogram 52system.membus.snoop_fanout::mean 0 # Request fanout histogram 53system.membus.snoop_fanout::stdev 0 # Request fanout histogram 54system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 57system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 58system.membus.snoop_fanout::min_value 0 # Request fanout histogram 59system.membus.snoop_fanout::max_value 0 # Request fanout histogram 60system.membus.snoop_fanout::total 2977330 # Request fanout histogram 61system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) 62system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 63system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) 64system.membus.respLayer1.utilization 0.3 # Layer utilization (%) | 38system.physmem.bw_total::total 32392098 # Total bandwidth to/from this memory (bytes/s) |
| 65system.cpu_clk_domain.clock 500 # Clock period in ticks 66system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 67system.cpu.workload.num_syscalls 46 # Number of system calls | 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 46 # Number of system calls |
| 68system.cpu.numCycles 11765161052 # number of cpu cycles simulated | 42system.cpu.numCycles 11765160797 # number of cpu cycles simulated |
| 69system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 70system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 71system.cpu.committedInsts 3008081022 # Number of instructions committed 72system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 73system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 74system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 75system.cpu.num_func_calls 33534539 # number of times a function call or return occured 76system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 81system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 82system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 83system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 84system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 85system.cpu.num_mem_refs 1677713084 # number of memory refs 86system.cpu.num_load_insts 1239184746 # Number of load instructions 87system.cpu.num_store_insts 438528338 # Number of store instructions 88system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 3008081022 # Number of instructions committed 46system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 33534539 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 59system.cpu.num_mem_refs 1677713084 # number of memory refs 60system.cpu.num_load_insts 1239184746 # Number of load instructions 61system.cpu.num_store_insts 438528338 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 89system.cpu.num_busy_cycles 11765161051.998001 # Number of busy cycles | 63system.cpu.num_busy_cycles 11765160796.998001 # Number of busy cycles |
| 90system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 91system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 92system.cpu.Branches 248500691 # Number of branches fetched 93system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 94system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 95system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 120system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 121system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 122system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 123system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 124system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 125system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 127system.cpu.op_class::total 4686862596 # Class of executed instruction | 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 248500691 # Number of branches fetched 67system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 68system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 69system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 70system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 71system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 94system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 98system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 4686862596 # Class of executed instruction |
| 102system.cpu.dcache.tags.replacements 9108581 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4084.587033 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 58853917000 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587033 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 120system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 127system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 132system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 133system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 134system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 135system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 136system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328499000 # number of ReadReq miss cycles 137system.cpu.dcache.ReadReq_miss_latency::total 143328499000 # number of ReadReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382147000 # number of WriteReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::total 57382147000 # number of WriteReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 200710646000 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 200710646000 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 200710646000 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 200710646000 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 150system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 153system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 155system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.759596 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.759596 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.703662 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.703662 # average WriteReq miss latency 164system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency 165system.cpu.dcache.demand_avg_miss_latency::total 22025.431824 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 22025.431824 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.dcache.fast_writes 0 # number of fast writes performed 175system.cpu.dcache.cache_copies 0 # number of cache copies performed 176system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks 177system.cpu.dcache.writebacks::total 3697956 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 182system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 183system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 184system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 185system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132494224000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.ReadReq_mshr_miss_latency::total 132494224000 # number of ReadReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54547406500 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.WriteReq_mshr_miss_latency::total 54547406500 # number of WriteReq MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187041630500 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.demand_mshr_miss_latency::total 187041630500 # number of demand (read+write) MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187041630500 # number of overall MSHR miss cycles 193system.cpu.dcache.overall_mshr_miss_latency::total 187041630500 # number of overall MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 199system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 201system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18343.759596 # average ReadReq mshr miss latency 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18343.759596 # average ReadReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28863.703662 # average WriteReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28863.703662 # average WriteReq mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency 210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 128system.cpu.icache.tags.replacements 10 # number of replacements 129system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use 130system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. 131system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 132system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. 133system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor 135system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy --- 11 unchanged lines hidden (view full) --- 147system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits 148system.cpu.icache.overall_hits::total 4013232207 # number of overall hits 149system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 150system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 151system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 152system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 153system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 154system.cpu.icache.overall_misses::total 675 # number of overall misses | 211system.cpu.icache.tags.replacements 10 # number of replacements 212system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use 213system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 217system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor 218system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy --- 11 unchanged lines hidden (view full) --- 230system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits 231system.cpu.icache.overall_hits::total 4013232207 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 237system.cpu.icache.overall_misses::total 675 # number of overall misses |
| 155system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles 156system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles 157system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles 158system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles 159system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles 160system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles | 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 37138500 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 37138500 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 37138500 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 37138500 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 37138500 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 37138500 # number of overall miss cycles |
| 161system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) 162system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) 163system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses 164system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses 165system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses 166system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses 167system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 169system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 170system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 171system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 172system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses | 244system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses |
| 173system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency 174system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency 175system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency 176system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency 177system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency 178system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency | 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55020 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 55020 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 55020 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 55020 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 55020 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 55020 # average overall miss latency |
| 179system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 180system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 182system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 183system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 184system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 185system.cpu.icache.fast_writes 0 # number of fast writes performed 186system.cpu.icache.cache_copies 0 # number of cache copies performed 187system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 188system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 189system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 190system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 191system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 192system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses | 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses |
| 193system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles 194system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles 195system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles 196system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles 197system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles 198system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles | 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36126000 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 36126000 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36126000 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 36126000 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36126000 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 36126000 # number of overall MSHR miss cycles |
| 199system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 200system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 201system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 202system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 203system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 204system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses | 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses |
| 205system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency 206system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency 207system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 208system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 209system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 210system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency | 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53520 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53520 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency |
| 211system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 212system.cpu.l2cache.tags.replacements 1926197 # number of replacements | 294system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.cpu.l2cache.tags.replacements 1926197 # number of replacements |
| 213system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use | 296system.cpu.l2cache.tags.tagsinuse 31136.249311 # Cycle average of tags in use |
| 214system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. 215system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. 216system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. | 297system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. 298system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. 299system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. |
| 217system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. 218system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor | 300system.cpu.l2cache.tags.warmup_cycle 340768621000 # Cycle when the warmup percentage was hit. 301system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795346 # Average occupied blocks per requestor |
| 219system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor | 302system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor |
| 220system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor | 303system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812949 # Average occupied blocks per requestor |
| 221system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy 222system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy 223system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy 224system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy 225system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id 226system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 227system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 228system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id --- 18 unchanged lines hidden (view full) --- 247system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses 248system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses 249system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 250system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses 251system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses 252system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 253system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses 254system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses | 304system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id --- 18 unchanged lines hidden (view full) --- 330system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses 331system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses 332system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 333system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses 334system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses 335system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 336system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses 337system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses |
| 255system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles 256system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles 257system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles 258system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles 259system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles 260system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles 261system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles 262system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles 263system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles 264system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles 265system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles | 338system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35451000 # number of ReadReq miss cycles 339system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61789308500 # number of ReadReq miss cycles 340system.cpu.l2cache.ReadReq_miss_latency::total 61824759500 # number of ReadReq miss cycles 341system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41017993500 # number of ReadExReq miss cycles 342system.cpu.l2cache.ReadExReq_miss_latency::total 41017993500 # number of ReadExReq miss cycles 343system.cpu.l2cache.demand_miss_latency::cpu.inst 35451000 # number of demand (read+write) miss cycles 344system.cpu.l2cache.demand_miss_latency::cpu.data 102807302000 # number of demand (read+write) miss cycles 345system.cpu.l2cache.demand_miss_latency::total 102842753000 # number of demand (read+write) miss cycles 346system.cpu.l2cache.overall_miss_latency::cpu.inst 35451000 # number of overall miss cycles 347system.cpu.l2cache.overall_miss_latency::cpu.data 102807302000 # number of overall miss cycles 348system.cpu.l2cache.overall_miss_latency::total 102842753000 # number of overall miss cycles |
| 266system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) 267system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) 268system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) 269system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses) 270system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses) 271system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 272system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 273system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 282system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses 283system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses 284system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 285system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses 286system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses 287system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 288system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses 289system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses | 349system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) 350system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) 351system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) 352system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses) 353system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 356system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 365system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses 366system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses 367system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 368system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses 369system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses 370system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 371system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses 372system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses |
| 290system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency 291system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency 292system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency 293system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency 294system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency 295system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency 296system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency 297system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency 298system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency 299system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency 300system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency | 373system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52520 # average ReadReq miss latency 374system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.009346 # average ReadReq miss latency 375system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.020805 # average ReadReq miss latency 376system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007680 # average ReadExReq miss latency 377system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007680 # average ReadExReq miss latency 378system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520 # average overall miss latency 379system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency 380system.cpu.l2cache.demand_avg_miss_latency::total 52500.015570 # average overall miss latency 381system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520 # average overall miss latency 382system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency 383system.cpu.l2cache.overall_avg_miss_latency::total 52500.015570 # average overall miss latency |
| 301system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 302system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 303system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 304system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 305system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 306system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 307system.cpu.l2cache.fast_writes 0 # number of fast writes performed 308system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 314system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses 315system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses 316system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 317system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses 318system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses 319system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 320system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses 321system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses | 384system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 385system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 386system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 387system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 388system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 389system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 390system.cpu.l2cache.fast_writes 0 # number of fast writes performed 391system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 397system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses 398system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses 399system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 400system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses 401system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses 402system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 403system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses 404system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses |
| 322system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles 323system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles 324system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles 325system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles 326system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles 327system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles 328system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles 329system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles 330system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles 331system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles 332system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles | 405system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27350500 # number of ReadReq MSHR miss cycles 406system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47666040500 # number of ReadReq MSHR miss cycles 407system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47693391000 # number of ReadReq MSHR miss cycles 408system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642453500 # number of ReadExReq MSHR miss cycles 409system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642453500 # number of ReadExReq MSHR miss cycles 410system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27350500 # number of demand (read+write) MSHR miss cycles 411system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79308494000 # number of demand (read+write) MSHR miss cycles 412system.cpu.l2cache.demand_mshr_miss_latency::total 79335844500 # number of demand (read+write) MSHR miss cycles 413system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27350500 # number of overall MSHR miss cycles 414system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79308494000 # number of overall MSHR miss cycles 415system.cpu.l2cache.overall_mshr_miss_latency::total 79335844500 # number of overall MSHR miss cycles |
| 333system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses 334system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses 335system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses 336system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses 337system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses 338system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 339system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses 340system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses 341system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 342system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses 343system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses | 416system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses 417system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses 418system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses 419system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses 420system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses 421system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 422system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses 423system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses 424system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 425system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses 426system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses |
| 344system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency 345system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency 346system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency 347system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency 348system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency 349system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency 350system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency 351system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency 352system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency 353system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency 354system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency | 427system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.259259 # average ReadReq mshr miss latency 428system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.009346 # average ReadReq mshr miss latency 429system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.020380 # average ReadReq mshr miss latency 430system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007680 # average ReadExReq mshr miss latency 431system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007680 # average ReadExReq mshr miss latency 432system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency 433system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency 434system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency 435system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency 436system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency 437system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency |
| 355system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 438system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 356system.cpu.dcache.tags.replacements 9108581 # number of replacements 357system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use 358system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 359system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 360system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 361system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. 362system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor 363system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 364system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy 365system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 366system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 367system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 368system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id 369system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id 370system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 371system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 372system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 373system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 374system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 375system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 376system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 377system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 378system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 379system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 380system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 381system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 382system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 383system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 384system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 385system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 386system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 387system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 388system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 389system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 390system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles 391system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles 392system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles 393system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles 394system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles 395system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles 396system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles 397system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles 398system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 402system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 403system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 404system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 405system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 407system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 409system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 410system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 411system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 412system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 413system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 414system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency 415system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency 416system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency 417system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency 418system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency 419system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency 420system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency 421system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency 422system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu.dcache.fast_writes 0 # number of fast writes performed 429system.cpu.dcache.cache_copies 0 # number of cache copies performed 430system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks 431system.cpu.dcache.writebacks::total 3697956 # number of writebacks 432system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 433system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 434system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 435system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 436system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 437system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 438system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 439system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 440system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles 441system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles 442system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles 443system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles 444system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles 445system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles 446system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles 447system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles 448system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 449system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 450system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 451system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 452system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 453system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 454system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 455system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 456system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency 457system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency 458system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency 459system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency 460system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 461system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 462system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 463system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 464system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 465system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 470system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 488system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram 490system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) 491system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 494system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 495system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) | 439system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution 442system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 444system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 462system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram 464system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) 465system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 466system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 467system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 468system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 469system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 470system.membus.trans_dist::ReadReq 1177614 # Transaction distribution 471system.membus.trans_dist::ReadResp 1177614 # Transaction distribution 472system.membus.trans_dist::Writeback 1018421 # Transaction distribution 473system.membus.trans_dist::ReadExReq 781295 # Transaction distribution 474system.membus.trans_dist::ReadExResp 781295 # Transaction distribution 475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) 476system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) 477system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) 478system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) 479system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) 480system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) 481system.membus.snoops 0 # Total snoops (count) 482system.membus.snoop_fanout::samples 2977330 # Request fanout histogram 483system.membus.snoop_fanout::mean 0 # Request fanout histogram 484system.membus.snoop_fanout::stdev 0 # Request fanout histogram 485system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 486system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram 487system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 488system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 489system.membus.snoop_fanout::min_value 0 # Request fanout histogram 490system.membus.snoop_fanout::max_value 0 # Request fanout histogram 491system.membus.snoop_fanout::total 2977330 # Request fanout histogram 492system.membus.reqLayer0.occupancy 7158077000 # Layer occupancy (ticks) 493system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 494system.membus.respLayer1.occupancy 9794545500 # Layer occupancy (ticks) 495system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
|
| 496 497---------- End Simulation Statistics ---------- | 496 497---------- End Simulation Statistics ---------- |