4,5c4,5
< sim_ticks 5901048931000 # Number of ticks simulated
< final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 5901048883000 # Number of ticks simulated
> final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 821481 # Simulator instruction rate (inst/s)
< host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1611526350 # Simulator tick rate (ticks/s)
< host_mem_usage 228472 # Number of bytes of host memory used
< host_seconds 3661.78 # Real time elapsed on the host
< sim_insts 3008081057 # Number of instructions simulated
< sim_ops 4686862651 # Number of ops (including micro ops) simulated
---
> host_inst_rate 766833 # Simulator instruction rate (inst/s)
> host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1504320663 # Simulator tick rate (ticks/s)
> host_mem_usage 233368 # Number of bytes of host memory used
> host_seconds 3922.73 # Real time elapsed on the host
> sim_insts 3008081022 # Number of instructions simulated
> sim_ops 4686862594 # Number of ops (including micro ops) simulated
38c38
< system.cpu.numCycles 11802097862 # number of cpu cycles simulated
---
> system.cpu.numCycles 11802097766 # number of cpu cycles simulated
41,43c41,43
< system.cpu.committedInsts 3008081057 # Number of instructions committed
< system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
---
> system.cpu.committedInsts 3008081022 # Number of instructions committed
> system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
46,47c46,47
< system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
< system.cpu.num_int_insts 4686862580 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
> system.cpu.num_int_insts 4686862523 # number of integer instructions
49,50c49,50
< system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
< system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read
> system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written
53,54c53,54
< system.cpu.num_mem_refs 1677713086 # number of memory refs
< system.cpu.num_load_insts 1239184749 # Number of load instructions
---
> system.cpu.num_mem_refs 1677713082 # number of memory refs
> system.cpu.num_load_insts 1239184745 # Number of load instructions
57c57
< system.cpu.num_busy_cycles 11802097862 # Number of busy cycles
---
> system.cpu.num_busy_cycles 11802097766 # Number of busy cycles
61,62c61,62
< system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use
< system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use
> system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
64c64
< system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
66c66
< system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor
69,74c69,74
< system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits
< system.cpu.icache.overall_hits::total 4013232252 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
> system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
87,92c87,92
< system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
139,140c139,140
< system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use
< system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use
> system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
143,144c143,144
< system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor
---
> system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor
147,148c147,148
< system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
151,154c151,154
< system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits
< system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
> system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
171,172c171,172
< system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
175,178c175,178
< system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
239c239
< system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use
243,244c243,244
< system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor
---
> system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor
246c246
< system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor
< sim_ticks 5901048931000 # Number of ticks simulated
< final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 5901048883000 # Number of ticks simulated
> final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 821481 # Simulator instruction rate (inst/s)
< host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1611526350 # Simulator tick rate (ticks/s)
< host_mem_usage 228472 # Number of bytes of host memory used
< host_seconds 3661.78 # Real time elapsed on the host
< sim_insts 3008081057 # Number of instructions simulated
< sim_ops 4686862651 # Number of ops (including micro ops) simulated
---
> host_inst_rate 766833 # Simulator instruction rate (inst/s)
> host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1504320663 # Simulator tick rate (ticks/s)
> host_mem_usage 233368 # Number of bytes of host memory used
> host_seconds 3922.73 # Real time elapsed on the host
> sim_insts 3008081022 # Number of instructions simulated
> sim_ops 4686862594 # Number of ops (including micro ops) simulated
38c38
< system.cpu.numCycles 11802097862 # number of cpu cycles simulated
---
> system.cpu.numCycles 11802097766 # number of cpu cycles simulated
41,43c41,43
< system.cpu.committedInsts 3008081057 # Number of instructions committed
< system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
---
> system.cpu.committedInsts 3008081022 # Number of instructions committed
> system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
46,47c46,47
< system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
< system.cpu.num_int_insts 4686862580 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
> system.cpu.num_int_insts 4686862523 # number of integer instructions
49,50c49,50
< system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
< system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read
> system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written
53,54c53,54
< system.cpu.num_mem_refs 1677713086 # number of memory refs
< system.cpu.num_load_insts 1239184749 # Number of load instructions
---
> system.cpu.num_mem_refs 1677713082 # number of memory refs
> system.cpu.num_load_insts 1239184745 # Number of load instructions
57c57
< system.cpu.num_busy_cycles 11802097862 # Number of busy cycles
---
> system.cpu.num_busy_cycles 11802097766 # Number of busy cycles
61,62c61,62
< system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use
< system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use
> system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
64c64
< system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
66c66
< system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor
69,74c69,74
< system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits
< system.cpu.icache.overall_hits::total 4013232252 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
> system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
87,92c87,92
< system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
139,140c139,140
< system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use
< system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use
> system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
143,144c143,144
< system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor
---
> system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor
147,148c147,148
< system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
151,154c151,154
< system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits
< system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
> system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
171,172c171,172
< system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
175,178c175,178
< system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
239c239
< system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use
243,244c243,244
< system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor
---
> system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor
246c246
< system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor