3,5c3,5
< sim_seconds 5.900695 # Number of seconds simulated
< sim_ticks 5900695290000 # Number of ticks simulated
< final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.901049 # Number of seconds simulated
> sim_ticks 5901048931000 # Number of ticks simulated
> final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1070782 # Simulator instruction rate (inst/s)
< host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2100461088 # Simulator tick rate (ticks/s)
< host_mem_usage 228516 # Number of bytes of host memory used
< host_seconds 2809.24 # Real time elapsed on the host
---
> host_inst_rate 821481 # Simulator instruction rate (inst/s)
> host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1611526350 # Simulator tick rate (ticks/s)
> host_mem_usage 228472 # Number of bytes of host memory used
> host_seconds 3661.78 # Real time elapsed on the host
27,28c27,28
< system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s)
31,33c31,33
< system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s)
35,36c35,36
< system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s)
38c38
< system.cpu.numCycles 11801390580 # number of cpu cycles simulated
---
> system.cpu.numCycles 11802097862 # number of cpu cycles simulated
57c57
< system.cpu.num_busy_cycles 11801390580 # Number of busy cycles
---
> system.cpu.num_busy_cycles 11802097862 # Number of busy cycles
61c61
< system.cpu.icache.tagsinuse 555.745205 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use
66c66
< system.cpu.icache.occ_blocks::cpu.inst 555.745205 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor
81,86c81,86
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles
99,104c99,104
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency
119,124c119,124
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles
131,136c131,136
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
139c139
< system.cpu.dcache.tagsinuse 4084.618409 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use
143,144c143,144
< system.cpu.dcache.warmup_cycle 58862653000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4084.618409 # Average occupied blocks per requestor
---
> system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor
163,170c163,170
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 159193930000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 59630900000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 59630900000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 218824830000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 218824830000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 218824830000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 218824830000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles
187,194c187,194
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 24013.232336 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 24013.232336 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency
213,220c213,220
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961419000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961419000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 191486799000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 191486799000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles
229,236c229,236
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
239c239
< system.cpu.l2cache.tagsinuse 30851.506102 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use
243,247c243,247
< system.cpu.l2cache.warmup_cycle 1317336331000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 14661.525978 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 21.582601 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 16168.397523 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.447434 # Average percentage of cache occupancy
---
> system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy
249,250c249,250
< system.cpu.l2cache.occ_percent::cpu.data 0.493420 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.941513 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy
< sim_seconds 5.900695 # Number of seconds simulated
< sim_ticks 5900695290000 # Number of ticks simulated
< final_tick 5900695290000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.901049 # Number of seconds simulated
> sim_ticks 5901048931000 # Number of ticks simulated
> final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1070782 # Simulator instruction rate (inst/s)
< host_op_rate 1668375 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2100461088 # Simulator tick rate (ticks/s)
< host_mem_usage 228516 # Number of bytes of host memory used
< host_seconds 2809.24 # Real time elapsed on the host
---
> host_inst_rate 821481 # Simulator instruction rate (inst/s)
> host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1611526350 # Simulator tick rate (ticks/s)
> host_mem_usage 228472 # Number of bytes of host memory used
> host_seconds 3661.78 # Real time elapsed on the host
27,28c27,28
< system.physmem.bw_read::cpu.data 23563932 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 23571253 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 23562520 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 23569841 # Total read bandwidth from this memory (bytes/s)
31,33c31,33
< system.physmem.bw_write::writebacks 11421342 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 11421342 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 11421342 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 11420657 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 11420657 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 11420657 # Total bandwidth to/from this memory (bytes/s)
35,36c35,36
< system.physmem.bw_total::cpu.data 23563932 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 34992595 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s)
38c38
< system.cpu.numCycles 11801390580 # number of cpu cycles simulated
---
> system.cpu.numCycles 11802097862 # number of cpu cycles simulated
57c57
< system.cpu.num_busy_cycles 11801390580 # Number of busy cycles
---
> system.cpu.num_busy_cycles 11802097862 # Number of busy cycles
61c61
< system.cpu.icache.tagsinuse 555.745205 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use
66c66
< system.cpu.icache.occ_blocks::cpu.inst 555.745205 # Average occupied blocks per requestor
---
> system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor
81,86c81,86
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 37868000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 37868000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 37868000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles
99,104c99,104
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 56100.740741 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 56100.740741 # average overall miss latency
119,124c119,124
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35843000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 35843000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35843000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 35843000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35843000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 35843000 # number of overall MSHR miss cycles
131,136c131,136
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
139c139
< system.cpu.dcache.tagsinuse 4084.618409 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use
143,144c143,144
< system.cpu.dcache.warmup_cycle 58862653000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4084.618409 # Average occupied blocks per requestor
---
> system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor
163,170c163,170
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 159193930000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 59630900000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 59630900000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 218824830000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 218824830000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 218824830000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 218824830000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 159195313000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 59631053000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 59631053000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 218826366000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles
187,194c187,194
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 24013.232336 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 24013.232336 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 24013.400892 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 24013.400892 # average overall miss latency
213,220c213,220
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961419000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961419000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 191486799000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 191486799000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961572000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961572000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 191488335000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 191488335000 # number of overall MSHR miss cycles
229,236c229,236
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
239c239
< system.cpu.l2cache.tagsinuse 30851.506102 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use
243,247c243,247
< system.cpu.l2cache.warmup_cycle 1317336331000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 14661.525978 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 21.582601 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 16168.397523 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.447434 # Average percentage of cache occupancy
---
> system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy
249,250c249,250
< system.cpu.l2cache.occ_percent::cpu.data 0.493420 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.941513 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.941512 # Average percentage of cache occupancy