3,5c3,5
< sim_seconds 5.895948 # Number of seconds simulated
< sim_ticks 5895947852500 # Number of ticks simulated
< final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.898831 # Number of seconds simulated
> sim_ticks 5898831348500 # Number of ticks simulated
> final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 735742 # Simulator instruction rate (inst/s)
< host_op_rate 1146353 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1442081312 # Simulator tick rate (ticks/s)
< host_mem_usage 269296 # Number of bytes of host memory used
< host_seconds 4088.50 # Real time elapsed on the host
---
> host_inst_rate 637466 # Simulator instruction rate (inst/s)
> host_op_rate 993229 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1250066735 # Simulator tick rate (ticks/s)
> host_mem_usage 275724 # Number of bytes of host memory used
> host_seconds 4718.81 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
< system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory
> system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
< system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory
25,40c25,40
< system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
44,45c44,45
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
47,48c47,48
< system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 11791895705 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 11797662697 # number of cpu cycles simulated
69c69
< system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles
---
> system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles
108c108
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
110c110
< system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use
114,115c114,115
< system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor
119,121c119,121
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id
127c127
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
144,151c144,151
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles
168,175c168,175
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency
182,183c182,183
< system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
< system.cpu.dcache.writebacks::total 3682716 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks
> system.cpu.dcache.writebacks::total 3669049 # number of writebacks
192,199c192,199
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles
208,216c208,216
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
218c218
< system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use
223,225c223,225
< system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy
232c232
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
245,250c245,250
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles
263,268c263,268
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency
283,288c283,288
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles
295,326c295,326
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 1919169 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 1938075 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits
329,338c329,338
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses
341,342c341,342
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses
344,345c344,345
< system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses
347,362c347,362
< system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses)
377,378c377,378
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses
381,382c381,382
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses
384,385c384,385
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses
387,400c387,400
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency
407,412c407,412
< system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
< system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks
> system.cpu.l2cache.writebacks::total 1032938 # number of writebacks
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses
415,416c415,416
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses
418,419c418,419
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses
421,434c421,434
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles
437,438c437,438
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses
441,442c441,442
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses
444,445c444,445
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses
447,460c447,460
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
464,465c464,465
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
467c467
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
469c469
< system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution
471c471
< system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution
480,486c480,486
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 65426496 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1938075 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram
488,489c488,489
< system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram
494,495c494,495
< system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks)
501,513c501,519
< system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
< system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
< system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
< system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 1176539 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution
> system.membus.trans_dist::CleanEvict 904164 # Transaction distribution
> system.membus.trans_dist::ReadExReq 793964 # Transaction distribution
> system.membus.trans_dist::ReadExResp 793964 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes)
516c522
< system.membus.snoop_fanout::samples 3870249 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 1970503 # Request fanout histogram
520c526
< system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram
525,526c531,532
< system.membus.snoop_fanout::total 3870249 # Request fanout histogram
< system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1970503 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks)
528c534
< system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks)
< sim_seconds 5.895948 # Number of seconds simulated
< sim_ticks 5895947852500 # Number of ticks simulated
< final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.898831 # Number of seconds simulated
> sim_ticks 5898831348500 # Number of ticks simulated
> final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 735742 # Simulator instruction rate (inst/s)
< host_op_rate 1146353 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1442081312 # Simulator tick rate (ticks/s)
< host_mem_usage 269296 # Number of bytes of host memory used
< host_seconds 4088.50 # Real time elapsed on the host
---
> host_inst_rate 637466 # Simulator instruction rate (inst/s)
> host_op_rate 993229 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1250066735 # Simulator tick rate (ticks/s)
> host_mem_usage 275724 # Number of bytes of host memory used
> host_seconds 4718.81 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
< system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory
> system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
< system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory
25,40c25,40
< system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
44,45c44,45
< system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
47,48c47,48
< system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 11791895705 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 11797662697 # number of cpu cycles simulated
69c69
< system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles
---
> system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles
108c108
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
110c110
< system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use
114,115c114,115
< system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor
119,121c119,121
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id
127c127
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
144,151c144,151
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles
168,175c168,175
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency
182,183c182,183
< system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
< system.cpu.dcache.writebacks::total 3682716 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks
> system.cpu.dcache.writebacks::total 3669049 # number of writebacks
192,199c192,199
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles
208,216c208,216
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
218c218
< system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use
223,225c223,225
< system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy
232c232
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
245,250c245,250
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles
263,268c263,268
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency
283,288c283,288
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles
295,326c295,326
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 1919169 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 1938075 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits
329,338c329,338
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses
341,342c341,342
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses
344,345c344,345
< system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses
347,362c347,362
< system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses)
377,378c377,378
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses
381,382c381,382
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses
384,385c384,385
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses
387,400c387,400
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency
407,412c407,412
< system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
< system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks
> system.cpu.l2cache.writebacks::total 1032938 # number of writebacks
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses
415,416c415,416
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses
418,419c418,419
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses
421,434c421,434
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles
437,438c437,438
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses
441,442c441,442
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses
444,445c444,445
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses
447,460c447,460
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
464,465c464,465
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
467c467
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
469c469
< system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution
471c471
< system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution
480,486c480,486
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 65426496 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1938075 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram
488,489c488,489
< system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram
494,495c494,495
< system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks)
501,513c501,519
< system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
< system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
< system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
< system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 1176539 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution
> system.membus.trans_dist::CleanEvict 904164 # Transaction distribution
> system.membus.trans_dist::ReadExReq 793964 # Transaction distribution
> system.membus.trans_dist::ReadExResp 793964 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes)
516c522
< system.membus.snoop_fanout::samples 3870249 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 1970503 # Request fanout histogram
520c526
< system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram
525,526c531,532
< system.membus.snoop_fanout::total 3870249 # Request fanout histogram
< system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1970503 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks)
528c534
< system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks)