1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.882581 # Number of seconds simulated
4sim_ticks 5882580526000 # Number of ticks simulated
5final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.882581 # Number of seconds simulated
4sim_ticks 5882580526000 # Number of ticks simulated
5final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 645050 # Simulator instruction rate (inst/s)
8host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1261455450 # Simulator tick rate (ticks/s)
10host_mem_usage 245540 # Number of bytes of host memory used
11host_seconds 4663.33 # Real time elapsed on the host
| 7host_inst_rate 876676 # Simulator instruction rate (inst/s)
8host_op_rate 1365940 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1714420225 # Simulator tick rate (ticks/s)
10host_mem_usage 249312 # Number of bytes of host memory used
11host_seconds 3431.24 # Real time elapsed on the host
|
12sim_insts 3008081022 # Number of instructions simulated
13sim_ops 4686862596 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
16system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory
20system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
37system.membus.throughput 32392097 # Throughput (bytes/s)
38system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
39system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
40system.membus.trans_dist::Writeback 1018421 # Transaction distribution
41system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
42system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
43system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
44system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
45system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
46system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
48system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
49system.membus.data_through_bus 190549120 # Total data (bytes)
50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
51system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
53system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
55system.cpu.workload.num_syscalls 46 # Number of system calls
56system.cpu.numCycles 11765161052 # number of cpu cycles simulated
57system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
58system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
59system.cpu.committedInsts 3008081022 # Number of instructions committed
60system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
| 12sim_insts 3008081022 # Number of instructions simulated
13sim_ops 4686862596 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory
16system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory
20system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
37system.membus.throughput 32392097 # Throughput (bytes/s)
38system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
39system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
40system.membus.trans_dist::Writeback 1018421 # Transaction distribution
41system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
42system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
43system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
44system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
45system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
46system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
48system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
49system.membus.data_through_bus 190549120 # Total data (bytes)
50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
51system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
53system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
55system.cpu.workload.num_syscalls 46 # Number of system calls
56system.cpu.numCycles 11765161052 # number of cpu cycles simulated
57system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
58system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
59system.cpu.committedInsts 3008081022 # Number of instructions committed
60system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
|
61system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses
| 61system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
|
62system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
63system.cpu.num_func_calls 33534539 # number of times a function call or return occured
64system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
| 62system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
63system.cpu.num_func_calls 33534539 # number of times a function call or return occured
64system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
|
65system.cpu.num_int_insts 4686862527 # number of integer instructions
| 65system.cpu.num_int_insts 4684368009 # number of integer instructions
|
66system.cpu.num_fp_insts 0 # number of float instructions
| 66system.cpu.num_fp_insts 0 # number of float instructions
|
67system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read
68system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written
| 67system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
68system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
|
69system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
70system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
| 69system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
70system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
| 71system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
72system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
|
71system.cpu.num_mem_refs 1677713084 # number of memory refs
72system.cpu.num_load_insts 1239184746 # Number of load instructions
73system.cpu.num_store_insts 438528338 # Number of store instructions
74system.cpu.num_idle_cycles 0 # Number of idle cycles
75system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
76system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
77system.cpu.idle_fraction 0 # Percentage of idle cycles
78system.cpu.icache.tags.replacements 10 # number of replacements
79system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
80system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
81system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
82system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
83system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
84system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
85system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
86system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
87system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
88system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
89system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
90system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
91system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
92system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
93system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
94system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
95system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
96system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
97system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
98system.cpu.icache.overall_misses::total 675 # number of overall misses
99system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
100system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
101system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
102system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
103system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
104system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
105system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
106system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
107system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
108system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
109system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
110system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
111system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
112system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
113system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
114system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
115system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
116system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
117system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
118system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
119system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
120system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
121system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
122system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency
123system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
124system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
125system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
126system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
127system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
128system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
129system.cpu.icache.fast_writes 0 # number of fast writes performed
130system.cpu.icache.cache_copies 0 # number of cache copies performed
131system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
132system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
133system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
134system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
135system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
136system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
137system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles
138system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles
139system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles
140system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles
141system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles
142system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles
143system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
144system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
145system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
146system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
147system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
148system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
149system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency
150system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency
151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
152system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
154system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
155system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
156system.cpu.l2cache.tags.replacements 1926197 # number of replacements
157system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
158system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
159system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
160system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
161system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
162system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
163system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
164system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
165system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
166system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
167system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
168system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy
169system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits
170system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits
171system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits
172system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits
173system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits
174system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits
175system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits
176system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits
177system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits
178system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits
179system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
180system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses
181system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses
182system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses
183system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses
184system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
185system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses
186system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses
187system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
188system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses
189system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses
190system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles
191system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles
192system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles
193system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles
194system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles
195system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles
196system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles
197system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles
198system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles
199system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles
200system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles
201system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
202system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
203system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
204system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses)
205system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses)
206system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
207system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
208system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses
209system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses
210system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses
211system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
212system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
213system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
214system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
215system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses
216system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses
217system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses
218system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses
219system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
220system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses
221system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses
222system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
223system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses
224system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses
225system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency
226system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency
227system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency
228system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency
229system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency
230system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
231system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
232system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency
233system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
234system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
235system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency
236system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
237system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
238system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
239system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
240system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
241system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
242system.cpu.l2cache.fast_writes 0 # number of fast writes performed
243system.cpu.l2cache.cache_copies 0 # number of cache copies performed
244system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks
245system.cpu.l2cache.writebacks::total 1018421 # number of writebacks
246system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
247system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses
248system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses
249system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses
250system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses
251system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
252system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses
253system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses
254system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
255system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses
256system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses
257system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles
258system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles
259system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles
260system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles
261system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles
262system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles
263system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles
264system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles
265system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles
266system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles
267system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles
268system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
269system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses
270system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses
271system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses
272system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses
273system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
274system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses
275system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses
276system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
277system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses
278system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses
279system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency
280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency
281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency
282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency
283system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency
284system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
286system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
287system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
288system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
289system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
290system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
291system.cpu.dcache.tags.replacements 9108581 # number of replacements
292system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
293system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
294system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
295system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
296system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
297system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
298system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
299system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
300system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
301system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
302system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
303system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
304system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
305system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
306system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
307system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
308system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
309system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
310system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
311system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
312system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
313system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
314system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
315system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
316system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
317system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
318system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
319system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
320system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
321system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
322system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
323system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
324system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
325system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
326system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
327system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
328system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
329system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
330system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
331system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
332system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
333system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
334system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
335system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
336system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
337system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
338system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
339system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
340system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
341system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
342system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
343system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
344system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
345system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
346system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
347system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency
348system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
349system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
350system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
351system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
352system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
353system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
354system.cpu.dcache.fast_writes 0 # number of fast writes performed
355system.cpu.dcache.cache_copies 0 # number of cache copies performed
356system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
357system.cpu.dcache.writebacks::total 3697956 # number of writebacks
358system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
359system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
360system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
361system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
362system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
363system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
364system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
365system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
366system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
367system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
368system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
369system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
370system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
371system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
372system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
373system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles
374system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
375system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
376system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
377system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
378system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
379system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
380system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
381system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
382system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
383system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
384system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
385system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
386system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
387system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
388system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
389system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
390system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
391system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s)
392system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
393system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
394system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
395system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
396system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
397system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
398system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
399system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
400system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
401system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
402system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
403system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
404system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
405system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
406system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
407system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
408system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
409system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
410system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
411
412---------- End Simulation Statistics ----------
| 73system.cpu.num_mem_refs 1677713084 # number of memory refs
74system.cpu.num_load_insts 1239184746 # Number of load instructions
75system.cpu.num_store_insts 438528338 # Number of store instructions
76system.cpu.num_idle_cycles 0 # Number of idle cycles
77system.cpu.num_busy_cycles 11765161052 # Number of busy cycles
78system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
79system.cpu.idle_fraction 0 # Percentage of idle cycles
80system.cpu.icache.tags.replacements 10 # number of replacements
81system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
82system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks.
83system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
84system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks.
85system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
86system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor
87system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy
88system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy
89system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
90system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
91system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
92system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
93system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
94system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
95system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
96system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
97system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
98system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
99system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
100system.cpu.icache.overall_misses::total 675 # number of overall misses
101system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
102system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
103system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
104system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
105system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
106system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
107system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
108system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
109system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
110system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
111system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
112system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
113system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
114system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
115system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
116system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
117system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
118system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
119system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
120system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
121system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
122system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
123system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
124system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency
125system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
126system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
127system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
128system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
129system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
130system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
131system.cpu.icache.fast_writes 0 # number of fast writes performed
132system.cpu.icache.cache_copies 0 # number of cache copies performed
133system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
134system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
135system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
136system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
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383system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
384system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
385system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
386system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
387system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
388system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
389system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
390system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
391system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
392system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
393system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s)
394system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
395system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
396system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
397system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
398system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
399system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
400system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
401system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
402system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
403system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
404system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
405system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
406system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
407system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
408system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
409system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
410system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
411system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
412system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
413
414---------- End Simulation Statistics ----------
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