Cross Reference: /gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11955:1170d039b31e )

full compact

stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.898831 # Number of seconds simulated 4sim_ticks 5898831348500 # Number of ticks simulated 5final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1175665 # Simulator instruction rate (inst/s) 8host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2305472192 # Simulator tick rate (ticks/s) 10host_mem_usage 275096 # Number of bytes of host memory used 11host_seconds 2558.62 # Real time elapsed on the host 12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory 19system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory 23system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.898831 # Number of seconds simulated 4sim_ticks 5898831348500 # Number of ticks simulated 5final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1175665 # Simulator instruction rate (inst/s) 8host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2305472192 # Simulator tick rate (ticks/s) 10host_mem_usage 275096 # Number of bytes of host memory used 11host_seconds 2558.62 # Real time elapsed on the host 12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory 19system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory 23system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
46system.cpu.workload.num_syscalls 46 # Number of system calls	46system.cpu.workload.numSyscalls 46 # Number of system calls
47system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states 48system.cpu.numCycles 11797662697 # number of cpu cycles simulated 49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51system.cpu.committedInsts 3008081022 # Number of instructions committed 52system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 53system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 55system.cpu.num_func_calls 33534539 # number of times a function call or return occured 56system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls 57system.cpu.num_int_insts 4684368009 # number of integer instructions 58system.cpu.num_fp_insts 0 # number of float instructions 59system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read 60system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written 61system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 62system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 63system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 64system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 65system.cpu.num_mem_refs 1677713084 # number of memory refs 66system.cpu.num_load_insts 1239184746 # Number of load instructions 67system.cpu.num_store_insts 438528338 # Number of store instructions 68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 69system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles 70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 72system.cpu.Branches 248500691 # Number of branches fetched 73system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 74system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 75system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 76system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 77system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction 78system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction 79system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction 80system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction 81system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction 82system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction 83system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction 84system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction 85system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction 86system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction 87system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction 88system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction 89system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction 90system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction 91system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction 92system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction 93system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction 94system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction 95system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction 98system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction 99system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction 100system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction 101system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction 102system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 105system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 106system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 107system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 110system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::total 4686862596 # Class of executed instruction 112system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 113system.cpu.dcache.tags.replacements 9108581 # number of replacements 114system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use 115system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 116system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 117system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 118system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor 120system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 121system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 123system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id 126system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id 127system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 128system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 129system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 130system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 131system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 132system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 133system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 134system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 135system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 136system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 137system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 138system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 139system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 140system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 141system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 142system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 143system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 144system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 145system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 146system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 147system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 148system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles 149system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles 150system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles 151system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles 152system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles 153system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles 154system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles 155system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles 156system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 157system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 158system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 159system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 160system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 168system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 169system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 170system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 171system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 172system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency 173system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency 174system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency 175system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency 176system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency 177system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency 179system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency 180system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 186system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks 187system.cpu.dcache.writebacks::total 3669049 # number of writebacks 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles 204system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 209system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 211system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency 220system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 221system.cpu.icache.tags.replacements 10 # number of replacements 222system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use 223system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor 228system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 233system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id 234system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses 235system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses 236system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 237system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits 238system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits 239system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits 240system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits 241system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits 242system.cpu.icache.overall_hits::total 4013232207 # number of overall hits 243system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 244system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 245system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 246system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 247system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 248system.cpu.icache.overall_misses::total 675 # number of overall misses 249system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles 250system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles 251system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles 252system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles 253system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles 254system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles 255system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) 256system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) 257system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses 258system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses 259system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses 260system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses 261system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 262system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 263system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 264system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 265system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 266system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 267system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency 268system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency 269system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency 270system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency 272system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency 273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 279system.cpu.icache.writebacks::writebacks 10 # number of writebacks 280system.cpu.icache.writebacks::total 10 # number of writebacks 281system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 282system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 283system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 284system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 285system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 286system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses 287system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles 288system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles 289system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles 290system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles 291system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles 292system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles 293system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 294system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 295system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 296system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 297system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 298system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency 305system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 306system.cpu.l2cache.tags.replacements 1938075 # number of replacements 307system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use 308system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. 312system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor 314system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor 315system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id 323system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id 325system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 326system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses 327system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses 328system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 329system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits 330system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits 331system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits 332system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits 333system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits 334system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits 335system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits 336system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits 337system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits 338system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits 339system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits 340system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits 341system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses 342system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses 343system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses 344system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses 345system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses 346system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses 347system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 348system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses 349system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses 350system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 351system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses 352system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses 353system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles 354system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles 355system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles 356system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles 357system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles 358system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles 359system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles 360system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles 361system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles 362system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles 363system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles 364system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles 365system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) 366system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) 367system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) 368system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) 369system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 370system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 371system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) 372system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) 373system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) 374system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) 375system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses 376system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses 378system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses 379system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses 380system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses 381system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses 382system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses 383system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 384system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 385system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses 386system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses 387system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 388system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses 389system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses 390system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 391system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses 392system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses 393system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 394system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency 396system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency 397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency 398system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency 399system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency 400system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency 401system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency 402system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency 404system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency 405system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks 412system.cpu.l2cache.writebacks::total 1032938 # number of writebacks 413system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses 414system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses 415system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses 416system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses 417system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses 418system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses 419system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses 420system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses 421system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 422system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses 423system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses 424system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 425system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses 426system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses 427system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles 428system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles 429system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles 430system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles 431system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles 432system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles 433system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles 434system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles 435system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles 436system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles 437system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles 438system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles 439system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 440system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 441system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses 442system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses 443system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 444system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 445system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses 446system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses 447system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 448system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses 449system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses 450system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 451system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses 452system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses 453system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 454system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 455system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency 456system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency 457system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency 458system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency 459system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency 460system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency 461system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency 462system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency 463system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency 464system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency 465system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. 466system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. 467system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 468system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter. 469system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 470system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 471system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 472system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution 480system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) 487system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) 488system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram 499system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) 500system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 501system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 502system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 503system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 504system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 505system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter. 506system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data. 507system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 508system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 509system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 510system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 511system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 512system.membus.trans_dist::ReadResp 1176539 # Transaction distribution 513system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution 514system.membus.trans_dist::CleanEvict 904164 # Transaction distribution 515system.membus.trans_dist::ReadExReq 793964 # Transaction distribution 516system.membus.trans_dist::ReadExResp 793964 # Transaction distribution 517system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution 518system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes) 519system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes) 520system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes) 521system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes) 522system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes) 523system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes) 524system.membus.snoops 0 # Total snoops (count) 525system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 526system.membus.snoop_fanout::samples 1970503 # Request fanout histogram 527system.membus.snoop_fanout::mean 0 # Request fanout histogram 528system.membus.snoop_fanout::stdev 0 # Request fanout histogram 529system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 530system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram 531system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 532system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 533system.membus.snoop_fanout::min_value 0 # Request fanout histogram 534system.membus.snoop_fanout::max_value 0 # Request fanout histogram 535system.membus.snoop_fanout::total 1970503 # Request fanout histogram 536system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks) 537system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 538system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks) 539system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 540 541---------- End Simulation Statistics ----------	47system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states 48system.cpu.numCycles 11797662697 # number of cpu cycles simulated 49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51system.cpu.committedInsts 3008081022 # Number of instructions committed 52system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 53system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 55system.cpu.num_func_calls 33534539 # number of times a function call or return occured 56system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls 57system.cpu.num_int_insts 4684368009 # number of integer instructions 58system.cpu.num_fp_insts 0 # number of float instructions 59system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read 60system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written 61system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 62system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 63system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 64system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 65system.cpu.num_mem_refs 1677713084 # number of memory refs 66system.cpu.num_load_insts 1239184746 # Number of load instructions 67system.cpu.num_store_insts 438528338 # Number of store instructions 68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 69system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles 70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 72system.cpu.Branches 248500691 # Number of branches fetched 73system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 74system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 75system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 76system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 77system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction 78system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction 79system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction 80system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction 81system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction 82system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction 83system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction 84system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction 85system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction 86system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction 87system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction 88system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction 89system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction 90system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction 91system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction 92system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction 93system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction 94system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction 95system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction 98system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction 99system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction 100system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction 101system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction 102system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 105system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 106system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 107system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 110system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::total 4686862596 # Class of executed instruction 112system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 113system.cpu.dcache.tags.replacements 9108581 # number of replacements 114system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use 115system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 116system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 117system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 118system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor 120system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 121system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 123system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id 126system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id 127system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 128system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 129system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 130system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 131system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 132system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 133system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 134system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 135system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 136system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 137system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 138system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 139system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 140system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 141system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 142system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 143system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 144system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 145system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 146system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 147system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 148system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles 149system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles 150system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles 151system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles 152system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles 153system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles 154system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles 155system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles 156system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 157system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 158system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 159system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 160system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 168system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 169system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 170system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 171system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 172system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency 173system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency 174system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency 175system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency 176system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency 177system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency 179system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency 180system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 186system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks 187system.cpu.dcache.writebacks::total 3669049 # number of writebacks 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles 204system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 209system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 211system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency 220system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 221system.cpu.icache.tags.replacements 10 # number of replacements 222system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use 223system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor 228system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 233system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id 234system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses 235system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses 236system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 237system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits 238system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits 239system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits 240system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits 241system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits 242system.cpu.icache.overall_hits::total 4013232207 # number of overall hits 243system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 244system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 245system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 246system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 247system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 248system.cpu.icache.overall_misses::total 675 # number of overall misses 249system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles 250system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles 251system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles 252system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles 253system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles 254system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles 255system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) 256system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) 257system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses 258system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses 259system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses 260system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses 261system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 262system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 263system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 264system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 265system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 266system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 267system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency 268system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency 269system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency 270system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency 272system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency 273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 279system.cpu.icache.writebacks::writebacks 10 # number of writebacks 280system.cpu.icache.writebacks::total 10 # number of writebacks 281system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 282system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 283system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 284system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 285system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 286system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses 287system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles 288system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles 289system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles 290system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles 291system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles 292system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles 293system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 294system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 295system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 296system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 297system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 298system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 299system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency 301system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency 303system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency 305system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 306system.cpu.l2cache.tags.replacements 1938075 # number of replacements 307system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use 308system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. 312system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor 314system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor 315system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy 318system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy 319system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id 322system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id 323system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id 325system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 326system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses 327system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses 328system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 329system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits 330system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits 331system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits 332system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits 333system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits 334system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits 335system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits 336system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits 337system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits 338system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits 339system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits 340system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits 341system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses 342system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses 343system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses 344system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses 345system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses 346system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses 347system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 348system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses 349system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses 350system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 351system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses 352system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses 353system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles 354system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles 355system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles 356system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles 357system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles 358system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles 359system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles 360system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles 361system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles 362system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles 363system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles 364system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles 365system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) 366system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) 367system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) 368system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) 369system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 370system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 371system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) 372system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) 373system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) 374system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) 375system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses 376system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses 378system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses 379system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses 380system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses 381system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses 382system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses 383system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 384system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 385system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses 386system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses 387system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 388system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses 389system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses 390system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 391system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses 392system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses 393system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 394system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency 396system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency 397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency 398system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency 399system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency 400system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency 401system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency 402system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency 404system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency 405system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks 412system.cpu.l2cache.writebacks::total 1032938 # number of writebacks 413system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses 414system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses 415system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses 416system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses 417system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses 418system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses 419system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses 420system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses 421system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 422system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses 423system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses 424system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 425system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses 426system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses 427system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles 428system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles 429system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles 430system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles 431system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles 432system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles 433system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles 434system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles 435system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles 436system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles 437system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles 438system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles 439system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 440system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 441system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses 442system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses 443system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 444system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 445system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses 446system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses 447system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 448system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses 449system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses 450system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 451system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses 452system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses 453system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 454system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 455system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency 456system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency 457system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency 458system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency 459system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency 460system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency 461system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency 462system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency 463system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency 464system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency 465system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. 466system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. 467system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 468system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter. 469system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 470system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 471system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 472system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution 480system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) 487system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) 488system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram 499system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) 500system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 501system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 502system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 503system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 504system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 505system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter. 506system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data. 507system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 508system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 509system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 510system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 511system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states 512system.membus.trans_dist::ReadResp 1176539 # Transaction distribution 513system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution 514system.membus.trans_dist::CleanEvict 904164 # Transaction distribution 515system.membus.trans_dist::ReadExReq 793964 # Transaction distribution 516system.membus.trans_dist::ReadExResp 793964 # Transaction distribution 517system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution 518system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes) 519system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes) 520system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes) 521system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes) 522system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes) 523system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes) 524system.membus.snoops 0 # Total snoops (count) 525system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 526system.membus.snoop_fanout::samples 1970503 # Request fanout histogram 527system.membus.snoop_fanout::mean 0 # Request fanout histogram 528system.membus.snoop_fanout::stdev 0 # Request fanout histogram 529system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 530system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram 531system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 532system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 533system.membus.snoop_fanout::min_value 0 # Request fanout histogram 534system.membus.snoop_fanout::max_value 0 # Request fanout histogram 535system.membus.snoop_fanout::total 1970503 # Request fanout histogram 536system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks) 537system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 538system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks) 539system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 540 541---------- End Simulation Statistics ----------