Cross Reference: /gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt

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stats.txt (10892:bd37e25fb3b7)	stats.txt (11138:a611a23c8cc2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882285 # Number of seconds simulated 4sim_ticks 5882284743500 # Number of ticks simulated 5final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882285 # Number of seconds simulated 4sim_ticks 5882284743500 # Number of ticks simulated 5final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 724530 # Simulator instruction rate (inst/s) 8host_op_rate 1128884 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1416814365 # Simulator tick rate (ticks/s) 10host_mem_usage 314268 # Number of bytes of host memory used 11host_seconds 4151.77 # Real time elapsed on the host	7host_inst_rate 704974 # Simulator instruction rate (inst/s) 8host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1378571885 # Simulator tick rate (ticks/s) 10host_mem_usage 317252 # Number of bytes of host memory used 11host_seconds 4266.94 # Real time elapsed on the host
12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124876416 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124919616 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65426432 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65426432 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1951194 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1951869 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1022288 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1022288 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 21229237 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 21236581 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11122622 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11122622 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11122622 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 21229237 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 32359203 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 46 # Number of system calls 42system.cpu.numCycles 11764569487 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 3008081022 # Number of instructions committed 46system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 33534539 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls 51system.cpu.num_int_insts 4684368009 # number of integer instructions 52system.cpu.num_fp_insts 0 # number of float instructions 53system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read 54system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 59system.cpu.num_mem_refs 1677713084 # number of memory refs 60system.cpu.num_load_insts 1239184746 # Number of load instructions 61system.cpu.num_store_insts 438528338 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 11764569486.998001 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 248500691 # Number of branches fetched 67system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 68system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 69system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 70system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 71system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction 75system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction 76system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction 77system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction 78system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction 79system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction 80system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction 81system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction 82system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction 83system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction 84system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction 85system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction 86system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction 87system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction 88system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction 89system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction 90system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction 91system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction 92system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction 93system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction 94system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 98system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 4686862596 # Class of executed instruction 102system.cpu.dcache.tags.replacements 9108581 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4084.586459 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 58853917500 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4084.586459 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997213 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997213 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 120system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 127system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 132system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 133system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 134system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 135system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 136system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000 # number of ReadReq miss cycles 137system.cpu.dcache.ReadReq_miss_latency::total 142985038000 # number of ReadReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::cpu.data 57429949000 # number of WriteReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::total 57429949000 # number of WriteReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 200414987000 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 200414987000 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 200414987000 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 200414987000 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 150system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 153system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 155system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041 # average WriteReq miss latency 164system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency 165system.cpu.dcache.demand_avg_miss_latency::total 21992.987022 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 21992.987022 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.dcache.fast_writes 0 # number of fast writes performed 175system.cpu.dcache.cache_copies 0 # number of cache copies performed 176system.cpu.dcache.writebacks::writebacks 3682721 # number of writebacks 177system.cpu.dcache.writebacks::total 3682721 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 182system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 183system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 184system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 185system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000 # number of ReadReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55540122000 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.WriteReq_mshr_miss_latency::total 55540122000 # number of WriteReq MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.demand_mshr_miss_latency::total 191302310000 # number of demand (read+write) MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000 # number of overall MSHR miss cycles 193system.cpu.dcache.overall_mshr_miss_latency::total 191302310000 # number of overall MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 199system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 201system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591 # average ReadReq mshr miss latency 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591 # average ReadReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041 # average WriteReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041 # average WriteReq mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency 210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 211system.cpu.icache.tags.replacements 10 # number of replacements 212system.cpu.icache.tags.tagsinuse 555.701425 # Cycle average of tags in use 213system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 217system.cpu.icache.tags.occ_blocks::cpu.inst 555.701425 # Average occupied blocks per requestor 218system.cpu.icache.tags.occ_percent::cpu.inst 0.271339 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_percent::total 0.271339 # Average percentage of cache occupancy 220system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses 226system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits 231system.cpu.icache.overall_hits::total 4013232207 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 237system.cpu.icache.overall_misses::total 675 # number of overall misses 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 37142500 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 37142500 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 37142500 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 37142500 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 37142500 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 37142500 # number of overall miss cycles 244system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 55025.925926 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 55025.925926 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36467500 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 36467500 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36467500 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 36467500 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36467500 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 36467500 # number of overall MSHR miss cycles 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency 294system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.cpu.l2cache.tags.replacements 1919162 # number of replacements 296system.cpu.l2cache.tags.tagsinuse 31136.006197 # Cycle average of tags in use 297system.cpu.l2cache.tags.total_refs 14382006 # Total number of references to valid blocks. 298system.cpu.l2cache.tags.sampled_refs 1948945 # Sample count of references to valid blocks. 299system.cpu.l2cache.tags.avg_refs 7.379380 # Average number of references to valid blocks. 300system.cpu.l2cache.tags.warmup_cycle 340768623000 # Cycle when the warmup percentage was hit. 301system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.605704 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_percent::writebacks 0.465892 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000781 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.data 0.483522 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::total 0.950196 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::2 997 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27920 # Occupied blocks per task id 314system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id 315system.cpu.l2cache.tags.tag_accesses 149614316 # Number of tag accesses 316system.cpu.l2cache.tags.data_accesses 149614316 # Number of data accesses 317system.cpu.l2cache.Writeback_hits::writebacks 3682721 # number of Writeback hits 318system.cpu.l2cache.Writeback_hits::total 3682721 # number of Writeback hits 319system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits 320system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits 321system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054089 # number of ReadSharedReq hits 322system.cpu.l2cache.ReadSharedReq_hits::total 6054089 # number of ReadSharedReq hits 323system.cpu.l2cache.demand_hits::cpu.data 7161483 # number of demand (read+write) hits 324system.cpu.l2cache.demand_hits::total 7161483 # number of demand (read+write) hits 325system.cpu.l2cache.overall_hits::cpu.data 7161483 # number of overall hits 326system.cpu.l2cache.overall_hits::total 7161483 # number of overall hits 327system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses 328system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses 329system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses 330system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses 331system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168761 # number of ReadSharedReq misses 332system.cpu.l2cache.ReadSharedReq_misses::total 1168761 # number of ReadSharedReq misses 333system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 334system.cpu.l2cache.demand_misses::cpu.data 1951194 # number of demand (read+write) misses 335system.cpu.l2cache.demand_misses::total 1951869 # number of demand (read+write) misses 336system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 337system.cpu.l2cache.overall_misses::cpu.data 1951194 # number of overall misses 338system.cpu.l2cache.overall_misses::total 1951869 # number of overall misses 339system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41077744500 # number of ReadExReq miss cycles 340system.cpu.l2cache.ReadExReq_miss_latency::total 41077744500 # number of ReadExReq miss cycles 341system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35453500 # number of ReadCleanReq miss cycles 342system.cpu.l2cache.ReadCleanReq_miss_latency::total 35453500 # number of ReadCleanReq miss cycles 343system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61359978500 # number of ReadSharedReq miss cycles 344system.cpu.l2cache.ReadSharedReq_miss_latency::total 61359978500 # number of ReadSharedReq miss cycles 345system.cpu.l2cache.demand_miss_latency::cpu.inst 35453500 # number of demand (read+write) miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.data 102437723000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::total 102473176500 # number of demand (read+write) miss cycles 348system.cpu.l2cache.overall_miss_latency::cpu.inst 35453500 # number of overall miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::total 102473176500 # number of overall miss cycles 351system.cpu.l2cache.Writeback_accesses::writebacks 3682721 # number of Writeback accesses(hits+misses) 352system.cpu.l2cache.Writeback_accesses::total 3682721 # number of Writeback accesses(hits+misses) 353system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) 356system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) 357system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) 358system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses 364system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses 365system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses 366system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses 367system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 368system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 369system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161814 # miss rate for ReadSharedReq accesses 370system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161814 # miss rate for ReadSharedReq accesses 371system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses 373system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses 374system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses 376system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses 377system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337 # average ReadExReq miss latency 378system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337 # average ReadExReq miss latency 379system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704 # average ReadCleanReq miss latency 380system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704 # average ReadCleanReq miss latency 381system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246 # average ReadSharedReq miss latency 382system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246 # average ReadSharedReq miss latency 383system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency 384system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency 385system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666 # average overall miss latency 389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.l2cache.fast_writes 0 # number of fast writes performed 396system.cpu.l2cache.cache_copies 0 # number of cache copies performed 397system.cpu.l2cache.writebacks::writebacks 1022288 # number of writebacks 398system.cpu.l2cache.writebacks::total 1022288 # number of writebacks 399system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 218 # number of CleanEvict MSHR misses 400system.cpu.l2cache.CleanEvict_mshr_misses::total 218 # number of CleanEvict MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses 402system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses 403system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses 404system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses 405system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168761 # number of ReadSharedReq MSHR misses 406system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168761 # number of ReadSharedReq MSHR misses 407system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 408system.cpu.l2cache.demand_mshr_misses::cpu.data 1951194 # number of demand (read+write) MSHR misses 409system.cpu.l2cache.demand_mshr_misses::total 1951869 # number of demand (read+write) MSHR misses 410system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 411system.cpu.l2cache.overall_mshr_misses::cpu.data 1951194 # number of overall MSHR misses 412system.cpu.l2cache.overall_mshr_misses::total 1951869 # number of overall MSHR misses 413system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33253414500 # number of ReadExReq MSHR miss cycles 414system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33253414500 # number of ReadExReq MSHR miss cycles 415system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28703500 # number of ReadCleanReq MSHR miss cycles 416system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28703500 # number of ReadCleanReq MSHR miss cycles 417system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49672368500 # number of ReadSharedReq MSHR miss cycles 418system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49672368500 # number of ReadSharedReq MSHR miss cycles 419system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28703500 # number of demand (read+write) MSHR miss cycles 420system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82925783000 # number of demand (read+write) MSHR miss cycles 421system.cpu.l2cache.demand_mshr_miss_latency::total 82954486500 # number of demand (read+write) MSHR miss cycles 422system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28703500 # number of overall MSHR miss cycles 423system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82925783000 # number of overall MSHR miss cycles 424system.cpu.l2cache.overall_mshr_miss_latency::total 82954486500 # number of overall MSHR miss cycles 425system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 426system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 427system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses 428system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses 429system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 430system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 431system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161814 # mshr miss rate for ReadSharedReq accesses 432system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161814 # mshr miss rate for ReadSharedReq accesses 433system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 434system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses 435system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses 436system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 437system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses 438system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses 439system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337 # average ReadExReq mshr miss latency 440system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337 # average ReadExReq mshr miss latency 441system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704 # average ReadCleanReq mshr miss latency 442system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704 # average ReadCleanReq mshr miss latency 443system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246 # average ReadSharedReq mshr miss latency 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency 451system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate	12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124876416 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124919616 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65426432 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65426432 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1951194 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1951869 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1022288 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1022288 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 21229237 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 21236581 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11122622 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11122622 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11122622 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 21229237 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 32359203 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 46 # Number of system calls 42system.cpu.numCycles 11764569487 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 3008081022 # Number of instructions committed 46system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 33534539 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls 51system.cpu.num_int_insts 4684368009 # number of integer instructions 52system.cpu.num_fp_insts 0 # number of float instructions 53system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read 54system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 59system.cpu.num_mem_refs 1677713084 # number of memory refs 60system.cpu.num_load_insts 1239184746 # Number of load instructions 61system.cpu.num_store_insts 438528338 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 11764569486.998001 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 248500691 # Number of branches fetched 67system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 68system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 69system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 70system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 71system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction 75system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction 76system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction 77system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction 78system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction 79system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction 80system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction 81system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction 82system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction 83system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction 84system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction 85system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction 86system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction 87system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction 88system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction 89system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction 90system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction 91system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction 92system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction 93system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction 94system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 98system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 4686862596 # Class of executed instruction 102system.cpu.dcache.tags.replacements 9108581 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4084.586459 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 58853917500 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4084.586459 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997213 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997213 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 120system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 127system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 132system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 133system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 134system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 135system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 136system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000 # number of ReadReq miss cycles 137system.cpu.dcache.ReadReq_miss_latency::total 142985038000 # number of ReadReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::cpu.data 57429949000 # number of WriteReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::total 57429949000 # number of WriteReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 200414987000 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 200414987000 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 200414987000 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 200414987000 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 150system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 153system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 155system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041 # average WriteReq miss latency 164system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency 165system.cpu.dcache.demand_avg_miss_latency::total 21992.987022 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 21992.987022 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.dcache.fast_writes 0 # number of fast writes performed 175system.cpu.dcache.cache_copies 0 # number of cache copies performed 176system.cpu.dcache.writebacks::writebacks 3682721 # number of writebacks 177system.cpu.dcache.writebacks::total 3682721 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 182system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 183system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 184system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 185system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000 # number of ReadReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55540122000 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.WriteReq_mshr_miss_latency::total 55540122000 # number of WriteReq MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.demand_mshr_miss_latency::total 191302310000 # number of demand (read+write) MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000 # number of overall MSHR miss cycles 193system.cpu.dcache.overall_mshr_miss_latency::total 191302310000 # number of overall MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 199system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 201system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591 # average ReadReq mshr miss latency 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591 # average ReadReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041 # average WriteReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041 # average WriteReq mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency 210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 211system.cpu.icache.tags.replacements 10 # number of replacements 212system.cpu.icache.tags.tagsinuse 555.701425 # Cycle average of tags in use 213system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 217system.cpu.icache.tags.occ_blocks::cpu.inst 555.701425 # Average occupied blocks per requestor 218system.cpu.icache.tags.occ_percent::cpu.inst 0.271339 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_percent::total 0.271339 # Average percentage of cache occupancy 220system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses 226system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits 231system.cpu.icache.overall_hits::total 4013232207 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 237system.cpu.icache.overall_misses::total 675 # number of overall misses 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 37142500 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 37142500 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 37142500 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 37142500 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 37142500 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 37142500 # number of overall miss cycles 244system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 55025.925926 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 55025.925926 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.fast_writes 0 # number of fast writes performed 269system.cpu.icache.cache_copies 0 # number of cache copies performed 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36467500 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 36467500 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36467500 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 36467500 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36467500 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 36467500 # number of overall MSHR miss cycles 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency 294system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 295system.cpu.l2cache.tags.replacements 1919162 # number of replacements 296system.cpu.l2cache.tags.tagsinuse 31136.006197 # Cycle average of tags in use 297system.cpu.l2cache.tags.total_refs 14382006 # Total number of references to valid blocks. 298system.cpu.l2cache.tags.sampled_refs 1948945 # Sample count of references to valid blocks. 299system.cpu.l2cache.tags.avg_refs 7.379380 # Average number of references to valid blocks. 300system.cpu.l2cache.tags.warmup_cycle 340768623000 # Cycle when the warmup percentage was hit. 301system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.605704 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_percent::writebacks 0.465892 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000781 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.data 0.483522 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::total 0.950196 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::2 997 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27920 # Occupied blocks per task id 314system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id 315system.cpu.l2cache.tags.tag_accesses 149614316 # Number of tag accesses 316system.cpu.l2cache.tags.data_accesses 149614316 # Number of data accesses 317system.cpu.l2cache.Writeback_hits::writebacks 3682721 # number of Writeback hits 318system.cpu.l2cache.Writeback_hits::total 3682721 # number of Writeback hits 319system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits 320system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits 321system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054089 # number of ReadSharedReq hits 322system.cpu.l2cache.ReadSharedReq_hits::total 6054089 # number of ReadSharedReq hits 323system.cpu.l2cache.demand_hits::cpu.data 7161483 # number of demand (read+write) hits 324system.cpu.l2cache.demand_hits::total 7161483 # number of demand (read+write) hits 325system.cpu.l2cache.overall_hits::cpu.data 7161483 # number of overall hits 326system.cpu.l2cache.overall_hits::total 7161483 # number of overall hits 327system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses 328system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses 329system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses 330system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses 331system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168761 # number of ReadSharedReq misses 332system.cpu.l2cache.ReadSharedReq_misses::total 1168761 # number of ReadSharedReq misses 333system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 334system.cpu.l2cache.demand_misses::cpu.data 1951194 # number of demand (read+write) misses 335system.cpu.l2cache.demand_misses::total 1951869 # number of demand (read+write) misses 336system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 337system.cpu.l2cache.overall_misses::cpu.data 1951194 # number of overall misses 338system.cpu.l2cache.overall_misses::total 1951869 # number of overall misses 339system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41077744500 # number of ReadExReq miss cycles 340system.cpu.l2cache.ReadExReq_miss_latency::total 41077744500 # number of ReadExReq miss cycles 341system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35453500 # number of ReadCleanReq miss cycles 342system.cpu.l2cache.ReadCleanReq_miss_latency::total 35453500 # number of ReadCleanReq miss cycles 343system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61359978500 # number of ReadSharedReq miss cycles 344system.cpu.l2cache.ReadSharedReq_miss_latency::total 61359978500 # number of ReadSharedReq miss cycles 345system.cpu.l2cache.demand_miss_latency::cpu.inst 35453500 # number of demand (read+write) miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.data 102437723000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::total 102473176500 # number of demand (read+write) miss cycles 348system.cpu.l2cache.overall_miss_latency::cpu.inst 35453500 # number of overall miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::total 102473176500 # number of overall miss cycles 351system.cpu.l2cache.Writeback_accesses::writebacks 3682721 # number of Writeback accesses(hits+misses) 352system.cpu.l2cache.Writeback_accesses::total 3682721 # number of Writeback accesses(hits+misses) 353system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) 356system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) 357system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) 358system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses 364system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses 365system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses 366system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses 367system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 368system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 369system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161814 # miss rate for ReadSharedReq accesses 370system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161814 # miss rate for ReadSharedReq accesses 371system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses 373system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses 374system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses 376system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses 377system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337 # average ReadExReq miss latency 378system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337 # average ReadExReq miss latency 379system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704 # average ReadCleanReq miss latency 380system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704 # average ReadCleanReq miss latency 381system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246 # average ReadSharedReq miss latency 382system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246 # average ReadSharedReq miss latency 383system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency 384system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency 385system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666 # average overall miss latency 389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.l2cache.fast_writes 0 # number of fast writes performed 396system.cpu.l2cache.cache_copies 0 # number of cache copies performed 397system.cpu.l2cache.writebacks::writebacks 1022288 # number of writebacks 398system.cpu.l2cache.writebacks::total 1022288 # number of writebacks 399system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 218 # number of CleanEvict MSHR misses 400system.cpu.l2cache.CleanEvict_mshr_misses::total 218 # number of CleanEvict MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses 402system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses 403system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses 404system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses 405system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168761 # number of ReadSharedReq MSHR misses 406system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168761 # number of ReadSharedReq MSHR misses 407system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 408system.cpu.l2cache.demand_mshr_misses::cpu.data 1951194 # number of demand (read+write) MSHR misses 409system.cpu.l2cache.demand_mshr_misses::total 1951869 # number of demand (read+write) MSHR misses 410system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 411system.cpu.l2cache.overall_mshr_misses::cpu.data 1951194 # number of overall MSHR misses 412system.cpu.l2cache.overall_mshr_misses::total 1951869 # number of overall MSHR misses 413system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33253414500 # number of ReadExReq MSHR miss cycles 414system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33253414500 # number of ReadExReq MSHR miss cycles 415system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28703500 # number of ReadCleanReq MSHR miss cycles 416system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28703500 # number of ReadCleanReq MSHR miss cycles 417system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49672368500 # number of ReadSharedReq MSHR miss cycles 418system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49672368500 # number of ReadSharedReq MSHR miss cycles 419system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28703500 # number of demand (read+write) MSHR miss cycles 420system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82925783000 # number of demand (read+write) MSHR miss cycles 421system.cpu.l2cache.demand_mshr_miss_latency::total 82954486500 # number of demand (read+write) MSHR miss cycles 422system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28703500 # number of overall MSHR miss cycles 423system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82925783000 # number of overall MSHR miss cycles 424system.cpu.l2cache.overall_mshr_miss_latency::total 82954486500 # number of overall MSHR miss cycles 425system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 426system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 427system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses 428system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses 429system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 430system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 431system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161814 # mshr miss rate for ReadSharedReq accesses 432system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161814 # mshr miss rate for ReadSharedReq accesses 433system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 434system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses 435system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses 436system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 437system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses 438system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses 439system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337 # average ReadExReq mshr miss latency 440system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337 # average ReadExReq mshr miss latency 441system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704 # average ReadCleanReq mshr miss latency 442system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704 # average ReadCleanReq mshr miss latency 443system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246 # average ReadSharedReq mshr miss latency 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency 451system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
	452system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
452system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 457system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution 458system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution 459system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) 460system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) 461system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) 462system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905472 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) 465system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) 466system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram	458system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution 465system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905472 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) 471system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) 472system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram
467system.cpu.toL2Bus.snoop_fanout::mean 1.095286 # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::stdev 0.293609 # Request fanout histogram	473system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram
469system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram	475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
470system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::1 18221943 90.47% 90.47% # Request fanout histogram 472system.cpu.toL2Bus.snoop_fanout::2 1919162 9.53% 100.00% # Request fanout histogram	476system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	479system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram	480system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram 477system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) 478system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 481system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 482system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 483system.membus.trans_dist::ReadResp 1169436 # Transaction distribution 484system.membus.trans_dist::Writeback 1022288 # Transaction distribution 485system.membus.trans_dist::CleanEvict 896090 # Transaction distribution 486system.membus.trans_dist::ReadExReq 782433 # Transaction distribution 487system.membus.trans_dist::ReadExResp 782433 # Transaction distribution 488system.membus.trans_dist::ReadSharedReq 1169436 # Transaction distribution 489system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822116 # Packet count per connected master and slave (bytes) 490system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822116 # Packet count per connected master and slave (bytes) 491system.membus.pkt_count::total 5822116 # Packet count per connected master and slave (bytes) 492system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346048 # Cumulative packet size per connected master and slave (bytes) 493system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346048 # Cumulative packet size per connected master and slave (bytes) 494system.membus.pkt_size::total 190346048 # Cumulative packet size per connected master and slave (bytes) 495system.membus.snoops 0 # Total snoops (count) 496system.membus.snoop_fanout::samples 3870262 # Request fanout histogram 497system.membus.snoop_fanout::mean 0 # Request fanout histogram 498system.membus.snoop_fanout::stdev 0 # Request fanout histogram 499system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 500system.membus.snoop_fanout::0 3870262 100.00% 100.00% # Request fanout histogram 501system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 502system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 503system.membus.snoop_fanout::min_value 0 # Request fanout histogram 504system.membus.snoop_fanout::max_value 0 # Request fanout histogram 505system.membus.snoop_fanout::total 3870262 # Request fanout histogram 506system.membus.reqLayer0.occupancy 7959418124 # Layer occupancy (ticks) 507system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 508system.membus.respLayer1.occupancy 9759348624 # Layer occupancy (ticks) 509system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 510 511---------- End Simulation Statistics ----------	482system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram 483system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) 484system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 485system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 486system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 487system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 488system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 489system.membus.trans_dist::ReadResp 1169436 # Transaction distribution 490system.membus.trans_dist::Writeback 1022288 # Transaction distribution 491system.membus.trans_dist::CleanEvict 896090 # Transaction distribution 492system.membus.trans_dist::ReadExReq 782433 # Transaction distribution 493system.membus.trans_dist::ReadExResp 782433 # Transaction distribution 494system.membus.trans_dist::ReadSharedReq 1169436 # Transaction distribution 495system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822116 # Packet count per connected master and slave (bytes) 496system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822116 # Packet count per connected master and slave (bytes) 497system.membus.pkt_count::total 5822116 # Packet count per connected master and slave (bytes) 498system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346048 # Cumulative packet size per connected master and slave (bytes) 499system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346048 # Cumulative packet size per connected master and slave (bytes) 500system.membus.pkt_size::total 190346048 # Cumulative packet size per connected master and slave (bytes) 501system.membus.snoops 0 # Total snoops (count) 502system.membus.snoop_fanout::samples 3870262 # Request fanout histogram 503system.membus.snoop_fanout::mean 0 # Request fanout histogram 504system.membus.snoop_fanout::stdev 0 # Request fanout histogram 505system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 506system.membus.snoop_fanout::0 3870262 100.00% 100.00% # Request fanout histogram 507system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 508system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 509system.membus.snoop_fanout::min_value 0 # Request fanout histogram 510system.membus.snoop_fanout::max_value 0 # Request fanout histogram 511system.membus.snoop_fanout::total 3870262 # Request fanout histogram 512system.membus.reqLayer0.occupancy 7959418124 # Layer occupancy (ticks) 513system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 514system.membus.respLayer1.occupancy 9759348624 # Layer occupancy (ticks) 515system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 516 517---------- End Simulation Statistics ----------