1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.895948 # Number of seconds simulated
4sim_ticks 5895947852500 # Number of ticks simulated
5final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1001702 # Simulator instruction rate (inst/s)
8host_op_rate 1560742 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1963371956 # Simulator tick rate (ticks/s)
10host_mem_usage 316648 # Number of bytes of host memory used
11host_seconds 3002.97 # Real time elapsed on the host
12sim_insts 3008081022 # Number of instructions simulated
13sim_ops 4686862596 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
19system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
23system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
--- 7 unchanged lines hidden (view full) ---
32system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
41system.cpu_clk_domain.clock 500 # Clock period in ticks
42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
46system.cpu.workload.num_syscalls 46 # Number of system calls
47system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
48system.cpu.numCycles 11791895705 # number of cpu cycles simulated
49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
51system.cpu.committedInsts 3008081022 # Number of instructions committed
52system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
53system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
55system.cpu.num_func_calls 33534539 # number of times a function call or return occured
--- 44 unchanged lines hidden (view full) ---
100system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
101system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
102system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
103system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
104system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
105system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
106system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
107system.cpu.op_class::total 4686862596 # Class of executed instruction
108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
109system.cpu.dcache.tags.replacements 9108581 # number of replacements
110system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
111system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
112system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
113system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
114system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
115system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
116system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
117system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
118system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
119system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
120system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
121system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
122system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
123system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
124system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
125system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
126system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
128system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
129system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
130system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
131system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
132system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
133system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
134system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
135system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
--- 72 unchanged lines hidden (view full) ---
208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
217system.cpu.icache.tags.replacements 10 # number of replacements
218system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
219system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
220system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
221system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
223system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
224system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
225system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
226system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
227system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
228system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
229system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
230system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
231system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
233system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
234system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
235system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
236system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
237system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
238system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
239system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
240system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
--- 52 unchanged lines hidden (view full) ---
293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
294system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
298system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
300system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
302system.cpu.l2cache.tags.replacements 1919169 # number of replacements
303system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
304system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
305system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
306system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
307system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
308system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
--- 6 unchanged lines hidden (view full) ---
316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
322system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
323system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
324system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
325system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
326system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
327system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
328system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
329system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
330system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
331system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
332system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
--- 126 unchanged lines hidden (view full) ---
459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
460system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
461system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
462system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
464system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
467system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
468system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
472system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
473system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
474system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
475system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution
--- 16 unchanged lines hidden (view full) ---
492system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
493system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
494system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
495system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
496system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
497system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
498system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
499system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
500system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
501system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
502system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
503system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
504system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
505system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
506system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
507system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
508system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
--- 21 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.895948 # Number of seconds simulated
4sim_ticks 5895947852500 # Number of ticks simulated
5final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1001702 # Simulator instruction rate (inst/s)
8host_op_rate 1560742 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1963371956 # Simulator tick rate (ticks/s)
10host_mem_usage 316648 # Number of bytes of host memory used
11host_seconds 3002.97 # Real time elapsed on the host
12sim_insts 3008081022 # Number of instructions simulated
13sim_ops 4686862596 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
19system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
23system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
--- 7 unchanged lines hidden (view full) ---
32system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
41system.cpu_clk_domain.clock 500 # Clock period in ticks
42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
46system.cpu.workload.num_syscalls 46 # Number of system calls
47system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
48system.cpu.numCycles 11791895705 # number of cpu cycles simulated
49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
51system.cpu.committedInsts 3008081022 # Number of instructions committed
52system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
53system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
54system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
55system.cpu.num_func_calls 33534539 # number of times a function call or return occured
--- 44 unchanged lines hidden (view full) ---
100system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
101system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
102system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
103system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
104system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
105system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
106system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
107system.cpu.op_class::total 4686862596 # Class of executed instruction
108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
109system.cpu.dcache.tags.replacements 9108581 # number of replacements
110system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
111system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
112system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
113system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
114system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
115system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
116system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
117system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
118system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
119system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
120system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
121system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
122system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
123system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
124system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
125system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
126system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
127system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
128system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
129system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
130system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
131system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
132system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
133system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
134system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
135system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
--- 72 unchanged lines hidden (view full) ---
208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
213system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
215system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
217system.cpu.icache.tags.replacements 10 # number of replacements
218system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
219system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
220system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
221system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
223system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
224system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
225system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
226system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
227system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
228system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
229system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
230system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
231system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
233system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
234system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
235system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
236system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits
237system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits
238system.cpu.icache.overall_hits::total 4013232207 # number of overall hits
239system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
240system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
--- 52 unchanged lines hidden (view full) ---
293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
294system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
298system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
300system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
302system.cpu.l2cache.tags.replacements 1919169 # number of replacements
303system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
304system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
305system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
306system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
307system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
308system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
309system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
--- 6 unchanged lines hidden (view full) ---
316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
322system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
323system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
324system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
325system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
326system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
327system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
328system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
329system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
330system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
331system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
332system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
--- 126 unchanged lines hidden (view full) ---
459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
460system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
461system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
462system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
464system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
467system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
468system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
469system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
470system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
471system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
472system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
473system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
474system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
475system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution
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492system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
493system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
494system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
495system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
496system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
497system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
498system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
499system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
500system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
501system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
502system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
503system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
504system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
505system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
506system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
507system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
508system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
--- 21 unchanged lines hidden ---