| config.ini (8835:7c68f84d7c4e) | config.ini (8983:8800b05e1cb3) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 |
| 19physmem=system.physmem | |
| 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 | 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 |
| 29system_port=system.membus.port[0] | 28system_port=system.membus.slave[0] |
| 30 31[system.cpu] 32type=TimingSimpleCPU 33children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 34checker=Null 35clock=500 36cpu_id=0 37defer_registration=false --- 16 unchanged lines hidden (view full) --- 54system=system 55tracer=system.cpu.tracer 56workload=system.cpu.workload 57dcache_port=system.cpu.dcache.cpu_side 58icache_port=system.cpu.icache.cpu_side 59 60[system.cpu.dcache] 61type=BaseCache | 29 30[system.cpu] 31type=TimingSimpleCPU 32children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 33checker=Null 34clock=500 35cpu_id=0 36defer_registration=false --- 16 unchanged lines hidden (view full) --- 53system=system 54tracer=system.cpu.tracer 55workload=system.cpu.workload 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache |
| 62addr_range=0:18446744073709551615 | 61addr_ranges=0:18446744073709551615 |
| 63assoc=2 64block_size=64 65forward_snoops=true 66hash_delay=1 67is_top_level=true 68latency=1000 69max_miss_count=0 70mshrs=10 --- 4 unchanged lines hidden (view full) --- 75size=262144 76subblock_size=0 77system=system 78tgts_per_mshr=5 79trace_addr=0 80two_queue=false 81write_buffers=8 82cpu_side=system.cpu.dcache_port | 62assoc=2 63block_size=64 64forward_snoops=true 65hash_delay=1 66is_top_level=true 67latency=1000 68max_miss_count=0 69mshrs=10 --- 4 unchanged lines hidden (view full) --- 74size=262144 75subblock_size=0 76system=system 77tgts_per_mshr=5 78trace_addr=0 79two_queue=false 80write_buffers=8 81cpu_side=system.cpu.dcache_port |
| 83mem_side=system.cpu.toL2Bus.port[1] | 82mem_side=system.cpu.toL2Bus.slave[1] |
| 84 85[system.cpu.dtb] 86type=X86TLB 87children=walker 88size=64 89walker=system.cpu.dtb.walker 90 91[system.cpu.dtb.walker] 92type=X86PagetableWalker 93system=system | 83 84[system.cpu.dtb] 85type=X86TLB 86children=walker 87size=64 88walker=system.cpu.dtb.walker 89 90[system.cpu.dtb.walker] 91type=X86PagetableWalker 92system=system |
| 94port=system.cpu.toL2Bus.port[3] | 93port=system.cpu.toL2Bus.slave[3] |
| 95 96[system.cpu.icache] 97type=BaseCache | 94 95[system.cpu.icache] 96type=BaseCache |
| 98addr_range=0:18446744073709551615 | 97addr_ranges=0:18446744073709551615 |
| 99assoc=2 100block_size=64 101forward_snoops=true 102hash_delay=1 103is_top_level=true 104latency=1000 105max_miss_count=0 106mshrs=10 --- 4 unchanged lines hidden (view full) --- 111size=131072 112subblock_size=0 113system=system 114tgts_per_mshr=5 115trace_addr=0 116two_queue=false 117write_buffers=8 118cpu_side=system.cpu.icache_port | 98assoc=2 99block_size=64 100forward_snoops=true 101hash_delay=1 102is_top_level=true 103latency=1000 104max_miss_count=0 105mshrs=10 --- 4 unchanged lines hidden (view full) --- 110size=131072 111subblock_size=0 112system=system 113tgts_per_mshr=5 114trace_addr=0 115two_queue=false 116write_buffers=8 117cpu_side=system.cpu.icache_port |
| 119mem_side=system.cpu.toL2Bus.port[0] | 118mem_side=system.cpu.toL2Bus.slave[0] |
| 120 121[system.cpu.interrupts] 122type=X86LocalApic 123int_latency=1000 124pio_addr=2305843009213693952 125pio_latency=1000 126system=system | 119 120[system.cpu.interrupts] 121type=X86LocalApic 122int_latency=1000 123pio_addr=2305843009213693952 124pio_latency=1000 125system=system |
| 127int_port=system.membus.port[4] 128pio=system.membus.port[3] | 126int_master=system.membus.slave[2] 127int_slave=system.membus.master[2] 128pio=system.membus.master[1] |
| 129 130[system.cpu.itb] 131type=X86TLB 132children=walker 133size=64 134walker=system.cpu.itb.walker 135 136[system.cpu.itb.walker] 137type=X86PagetableWalker 138system=system | 129 130[system.cpu.itb] 131type=X86TLB 132children=walker 133size=64 134walker=system.cpu.itb.walker 135 136[system.cpu.itb.walker] 137type=X86PagetableWalker 138system=system |
| 139port=system.cpu.toL2Bus.port[2] | 139port=system.cpu.toL2Bus.slave[2] |
| 140 141[system.cpu.l2cache] 142type=BaseCache | 140 141[system.cpu.l2cache] 142type=BaseCache |
| 143addr_range=0:18446744073709551615 | 143addr_ranges=0:18446744073709551615 |
| 144assoc=2 145block_size=64 146forward_snoops=true 147hash_delay=1 148is_top_level=false 149latency=10000 150max_miss_count=0 151mshrs=10 152prefetch_on_access=false 153prefetcher=Null 154prioritizeRequests=false 155repl=Null 156size=2097152 157subblock_size=0 158system=system 159tgts_per_mshr=5 160trace_addr=0 161two_queue=false 162write_buffers=8 | 144assoc=2 145block_size=64 146forward_snoops=true 147hash_delay=1 148is_top_level=false 149latency=10000 150max_miss_count=0 151mshrs=10 152prefetch_on_access=false 153prefetcher=Null 154prioritizeRequests=false 155repl=Null 156size=2097152 157subblock_size=0 158system=system 159tgts_per_mshr=5 160trace_addr=0 161two_queue=false 162write_buffers=8 |
| 163cpu_side=system.cpu.toL2Bus.port[4] 164mem_side=system.membus.port[2] | 163cpu_side=system.cpu.toL2Bus.master[0] 164mem_side=system.membus.slave[1] |
| 165 166[system.cpu.toL2Bus] 167type=Bus 168block_size=64 169bus_id=0 170clock=1000 171header_cycles=1 172use_default_range=false 173width=64 | 165 166[system.cpu.toL2Bus] 167type=Bus 168block_size=64 169bus_id=0 170clock=1000 171header_cycles=1 172use_default_range=false 173width=64 |
| 174port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side | 174master=system.cpu.l2cache.cpu_side 175slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 175 176[system.cpu.tracer] 177type=ExeTracer 178 179[system.cpu.workload] 180type=LiveProcess 181cmd=bzip2 input.source 1 | 176 177[system.cpu.tracer] 178type=ExeTracer 179 180[system.cpu.workload] 181type=LiveProcess 182cmd=bzip2 input.source 1 |
| 182cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing | 183cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing |
| 183egid=100 184env= 185errout=cerr 186euid=100 187executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 188gid=100 189input=cin 190max_stack_size=67108864 --- 7 unchanged lines hidden (view full) --- 198[system.membus] 199type=Bus 200block_size=64 201bus_id=0 202clock=1000 203header_cycles=1 204use_default_range=false 205width=64 | 184egid=100 185env= 186errout=cerr 187euid=100 188executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 189gid=100 190input=cin 191max_stack_size=67108864 --- 7 unchanged lines hidden (view full) --- 199[system.membus] 200type=Bus 201block_size=64 202bus_id=0 203clock=1000 204header_cycles=1 205use_default_range=false 206width=64 |
| 206port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port | 207master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave 208slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master |
| 207 208[system.physmem] | 209 210[system.physmem] |
| 209type=PhysicalMemory | 211type=SimpleMemory 212conf_table_reported=false |
| 210file= | 213file= |
| 214in_addr_map=true |
|
| 211latency=30000 212latency_var=0 213null=false 214range=0:134217727 215zero=false | 215latency=30000 216latency_var=0 217null=false 218range=0:134217727 219zero=false |
| 216port=system.membus.port[1] | 220port=system.membus.master[0] |
| 217 | 221 |