| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.431420 # Number of seconds simulated 4sim_ticks 2431419954000 # Number of ticks simulated 5final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.431420 # Number of seconds simulated 4sim_ticks 2431419954000 # Number of ticks simulated 5final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1812626 # Simulator instruction rate (inst/s) 8host_op_rate 2022908 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2864161367 # Simulator tick rate (ticks/s) 10host_mem_usage 223004 # Number of bytes of host memory used 11host_seconds 848.91 # Real time elapsed on the host | 7host_inst_rate 629125 # Simulator instruction rate (inst/s) 8host_op_rate 702110 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 994091440 # Simulator tick rate (ticks/s) 10host_mem_usage 230132 # Number of bytes of host memory used 11host_seconds 2445.87 # Real time elapsed on the host |
| 12sim_insts 1538759609 # Number of instructions simulated 13sim_ops 1717270343 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 172766016 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 75006720 # Number of bytes written to this memory 17system.physmem.num_reads 2699469 # Number of read requests responded to by this memory 18system.physmem.num_writes 1171980 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 104 unchanged lines hidden (view full) --- 124system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency 126system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency 127system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency 128system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 1538759609 # Number of instructions simulated 13sim_ops 1717270343 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 172766016 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 75006720 # Number of bytes written to this memory 17system.physmem.num_reads 2699469 # Number of read requests responded to by this memory 18system.physmem.num_writes 1171980 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 104 unchanged lines hidden (view full) --- 124system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency 126system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency 127system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency 128system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 132system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 133system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 132system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 134system.cpu.icache.fast_writes 0 # number of fast writes performed 135system.cpu.icache.cache_copies 0 # number of cache copies performed 136system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 137system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 138system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 139system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 140system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 141system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses --- 66 unchanged lines hidden (view full) --- 208system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency 209system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency 210system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency 211system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency 212system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 215system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 134system.cpu.icache.fast_writes 0 # number of fast writes performed 135system.cpu.icache.cache_copies 0 # number of cache copies performed 136system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 137system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 138system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 139system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 140system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 141system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses --- 66 unchanged lines hidden (view full) --- 208system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency 209system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency 210system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency 211system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency 212system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 215system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 216system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 217system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 216system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 217system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 218system.cpu.dcache.fast_writes 0 # number of fast writes performed 219system.cpu.dcache.cache_copies 0 # number of cache copies performed 220system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks 221system.cpu.dcache.writebacks::total 3061985 # number of writebacks 222system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses 223system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses 224system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 225system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses --- 92 unchanged lines hidden (view full) --- 318system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 319system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 320system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 321system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 322system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 324system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 325system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 218system.cpu.dcache.fast_writes 0 # number of fast writes performed 219system.cpu.dcache.cache_copies 0 # number of cache copies performed 220system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks 221system.cpu.dcache.writebacks::total 3061985 # number of writebacks 222system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses 223system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses 224system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 225system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses --- 92 unchanged lines hidden (view full) --- 318system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 319system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 320system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 321system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 322system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 323system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 324system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 325system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 326system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 327system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 326system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 327system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 328system.cpu.l2cache.fast_writes 0 # number of fast writes performed 329system.cpu.l2cache.cache_copies 0 # number of cache copies performed 330system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks 331system.cpu.l2cache.writebacks::total 1171980 # number of writebacks 332system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 333system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses 334system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses 335system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses --- 35 unchanged lines hidden --- | 328system.cpu.l2cache.fast_writes 0 # number of fast writes performed 329system.cpu.l2cache.cache_copies 0 # number of cache copies performed 330system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks 331system.cpu.l2cache.writebacks::total 1171980 # number of writebacks 332system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 333system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses 334system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses 335system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses --- 35 unchanged lines hidden --- |