Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.377030 # Number of seconds simulated
4sim_ticks 2377029670500 # Number of ticks simulated
5final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.379922 # Number of seconds simulated
4sim_ticks 2379921906500 # Number of ticks simulated
5final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 744525 # Simulator instruction rate (inst/s)
8host_op_rate 802329 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1150119113 # Simulator tick rate (ticks/s)
10host_mem_usage 266344 # Number of bytes of host memory used
11host_seconds 2066.77 # Real time elapsed on the host

7host_inst_rate 802178 # Simulator instruction rate (inst/s)
8host_op_rate 864460 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1240688848 # Simulator tick rate (ticks/s)
10host_mem_usage 272000 # Number of bytes of host memory used
11host_seconds 1918.23 # Real time elapsed on the host

12sim_insts 1538759602 # Number of instructions simulated
13sim_ops 1658228915 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
19system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory
19system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory

20system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory

22system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
23system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory

22system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory
23system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory

24system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory

25system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

25system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory
26system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory
28system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s)
40system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

41system.cpu_clk_domain.clock 500 # Clock period in ticks

42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

73system.cpu.dtb.walker.walks 0 # Table walker walks requested
74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
96system.cpu.dtb.read_accesses 0 # DTB read accesses
97system.cpu.dtb.write_accesses 0 # DTB write accesses
98system.cpu.dtb.inst_accesses 0 # ITB inst accesses
99system.cpu.dtb.hits 0 # DTB hits
100system.cpu.dtb.misses 0 # DTB misses
101system.cpu.dtb.accesses 0 # DTB accesses

102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

133system.cpu.itb.walker.walks 0 # Table walker walks requested
134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
156system.cpu.itb.read_accesses 0 # DTB read accesses
157system.cpu.itb.write_accesses 0 # DTB write accesses
158system.cpu.itb.inst_accesses 0 # ITB inst accesses
159system.cpu.itb.hits 0 # DTB hits
160system.cpu.itb.misses 0 # DTB misses
161system.cpu.itb.accesses 0 # DTB accesses
162system.cpu.workload.num_syscalls 46 # Number of system calls

163system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states
164system.cpu.numCycles 4754059341 # number of cpu cycles simulated

163system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states
164system.cpu.numCycles 4759843813 # number of cpu cycles simulated

165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
167system.cpu.committedInsts 1538759602 # Number of instructions committed
168system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed
169system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
170system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
171system.cpu.num_func_calls 27330256 # number of times a function call or return occured
172system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

177system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
178system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
179system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read
180system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
181system.cpu.num_mem_refs 633153380 # number of memory refs
182system.cpu.num_load_insts 458306334 # Number of load instructions
183system.cpu.num_store_insts 174847046 # Number of store instructions
184system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

185system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles

185system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles

186system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
187system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
188system.cpu.Branches 213462427 # Number of branches fetched
189system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
190system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
191system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
192system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
193system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

216system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
217system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
218system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
219system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
220system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
221system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
222system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
223system.cpu.op_class::total 1664032481 # Class of executed instruction

224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

225system.cpu.dcache.tags.replacements 9111140 # number of replacements

226system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use

226system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use

227system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
228system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
229system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.

230system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
231system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
232system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
233system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy

230system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit.
231system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor
232system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy
233system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy

234system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id

235system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
236system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
237system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id

235system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
236system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
237system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id

238system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
239system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
240system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
241system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
242system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses

243system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

243system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

244system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
245system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
246system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
247system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
248system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
249system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
250system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
251system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits

--- 6 unchanged lines hidden (view full) ---

258system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
259system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
260system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
261system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
262system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
263system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
264system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
265system.cpu.dcache.overall_misses::total 9115236 # number of overall misses

266system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
267system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
268system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
269system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
270system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
271system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
272system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
273system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles

266system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles
267system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles
268system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles
269system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles
270system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles
271system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles
272system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles
273system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles

274system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
275system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
276system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
277system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
278system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
279system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
280system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
281system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

290system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
291system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
292system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
293system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
294system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
295system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
296system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
297system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses

298system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
299system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
300system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
301system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
302system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
303system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
304system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
305system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency

298system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency
299system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency
300system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency
301system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency
302system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency
303system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency
304system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency
305system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency

306system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
307system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
308system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
309system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
310system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
311system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

312system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
313system.cpu.dcache.writebacks::total 3681379 # number of writebacks

312system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks
313system.cpu.dcache.writebacks::total 3667054 # number of writebacks

314system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
315system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
316system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
317system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
318system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
319system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
320system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
321system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
322system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
323system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses

324system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
325system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
327system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
328system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
329system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
330system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
331system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles

324system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles
325system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles
326system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles
327system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles
328system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
329system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
330system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles
331system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles
332system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles
333system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles

334system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
335system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
336system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
337system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
338system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
339system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
340system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
341system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
342system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
343system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses

344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

344system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency
345system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency
346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency
347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency
348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency
351system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency
352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency
353system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency
354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

355system.cpu.icache.tags.replacements 7 # number of replacements

356system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use

356system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use

357system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
358system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
359system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

361system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
362system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
363system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy

361system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor
362system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy
363system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy

364system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
365system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
366system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
367system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
368system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
369system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
370system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses

371system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

371system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

372system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
373system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
374system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
375system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits
376system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits
377system.cpu.icache.overall_hits::total 1544564953 # number of overall hits
378system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
379system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
380system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
381system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
382system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
383system.cpu.icache.overall_misses::total 638 # number of overall misses

384system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
385system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
386system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
387system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
388system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
389system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles

384system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles
385system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles
386system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles
387system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles
388system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles
389system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles

390system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
391system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
392system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
393system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses
394system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses
395system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses
396system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
397system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
398system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
399system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
400system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
401system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses

402system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
403system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
404system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
405system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
406system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
407system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency

402system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency
403system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency
404system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
405system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency
406system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
407system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency

408system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
409system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
410system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
411system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
412system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
413system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
414system.cpu.icache.writebacks::writebacks 7 # number of writebacks
415system.cpu.icache.writebacks::total 7 # number of writebacks
416system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
417system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
418system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
419system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
420system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
421system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses

422system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
423system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
424system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
425system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
426system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
427system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles

422system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles
423system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles
424system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles
425system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles
426system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles
427system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles

428system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
429system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
430system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
431system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
432system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
433system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses

434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
440system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
441system.cpu.l2cache.tags.replacements 1919027 # number of replacements
442system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
443system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
444system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
445system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
446system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
447system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
448system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
450system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
452system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
453system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
454system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
456system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
457system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
458system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
459system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
460system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
461system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
462system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
463system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
464system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
465system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits

434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency
435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency
436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
437system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
439system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
440system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
441system.cpu.l2cache.tags.replacements 1938113 # number of replacements
442system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use
443system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks.
444system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks.
445system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks.
446system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit.
447system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor
448system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor
449system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor
450system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy
452system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy
453system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy
454system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
456system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id
457system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id
458system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id
459system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id
460system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
461system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses
462system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses
463system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
464system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits
465system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits

466system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
467system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits

468system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
469system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits

468system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits
469system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits

470system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
471system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits

472system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
473system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits

472system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits
473system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits

474system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits

475system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits

475system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits

477system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits

478system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
479system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
480system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
481system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses

478system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits
479system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits
480system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses
481system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses

482system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses
483system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses

484system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
485system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses

484system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses
485system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses

486system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses

487system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
488system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses

487system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses
488system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses

489system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses

490system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
491system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
492system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
493system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
494system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
495system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
496system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
497system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
498system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
501system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
504system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
505system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)

490system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses
491system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses
492system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles
493system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles
494system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles
495system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles
496system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles
497system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles
498system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles
499system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles
500system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles
501system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles
502system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles
503system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles
504system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses)
505system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses)

506system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
507system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
508system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
509system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
510system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses)
511system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses)
512system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses)
513system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses)
514system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses

520system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
521system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses

520system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses
521system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses

522system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses
523system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses

524system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
525system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses

524system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses
525system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses

526system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses

527system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
528system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses

527system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses
528system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses

529system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses

530system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
531system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
532system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
533system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
534system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
535system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
536system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
537system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
538system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
543system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency

530system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses
531system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses
532system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency
533system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency
534system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency
535system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency
536system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency
537system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency
538system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
539system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
540system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency
541system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
542system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
543system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency

544system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
545system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
546system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
547system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
548system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
549system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

550system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
551system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
552system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
553system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
554system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
555system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses

550system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks
551system.cpu.l2cache.writebacks::total 1031709 # number of writebacks
552system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses
553system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses
554system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses
555system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses

556system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses
557system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses

558system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
559system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses

558system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses
559system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses

560system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses

561system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
562system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses

561system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses
562system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses

563system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses

564system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
565system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
566system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
567system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
568system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
569system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
570system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
571system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
572system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles

564system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses
565system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses
566system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles
567system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles
568system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles
569system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles
570system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles
571system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles
572system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles
573system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles
574system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles
575system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles
576system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles

578system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
579system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

580system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
581system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses

580system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses
581system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses

582system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses
583system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses

584system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
585system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses

584system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses
585system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses

586system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses

587system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
588system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses

587system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses
588system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses

589system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses

590system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
591system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
592system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
593system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
594system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
595system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
596system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
597system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
598system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
599system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
600system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
601system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
602system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
603system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency

590system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses
591system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses
592system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency
593system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency
594system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency
595system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency
596system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency
597system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency
598system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
599system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
600system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
601system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
602system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
603system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency

604system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
605system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
606system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

607system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
608system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

607system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter.
608system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

609system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

610system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states

610system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states

611system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution

612system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution

612system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution

613system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution

614system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution

614system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution

615system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
616system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
617system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
618system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
619system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
620system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes)
621system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes)
622system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes)

623system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
624system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
625system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
626system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes)
627system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
628system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram

623system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes)
624system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes)
625system.cpu.toL2Bus.snoops 1938113 # Total snoops (count)
626system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes)
627system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram
628system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram

630system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

631system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram

631system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram

633system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
634system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
635system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
636system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

637system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
638system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)

637system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram
638system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks)

639system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
640system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
641system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
642system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
643system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)

644system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
645system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
646system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
647system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
648system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
649system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
650system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
651system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
652system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
653system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
654system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)

644system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter.
645system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
646system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
647system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
648system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
649system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
650system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
651system.membus.trans_dist::ReadResp 1176874 # Transaction distribution
652system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution
653system.membus.trans_dist::CleanEvict 905404 # Transaction distribution
654system.membus.trans_dist::ReadExReq 793696 # Transaction distribution
655system.membus.trans_dist::ReadExResp 793696 # Transaction distribution
656system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution
657system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes)
658system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes)
659system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes)
660system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes)

655system.membus.snoops 0 # Total snoops (count)
656system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

661system.membus.snoops 0 # Total snoops (count)
662system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

657system.membus.snoop_fanout::samples 3869897 # Request fanout histogram

663system.membus.snoop_fanout::samples 1970570 # Request fanout histogram

658system.membus.snoop_fanout::mean 0 # Request fanout histogram
659system.membus.snoop_fanout::stdev 0 # Request fanout histogram
660system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

664system.membus.snoop_fanout::mean 0 # Request fanout histogram
665system.membus.snoop_fanout::stdev 0 # Request fanout histogram
666system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

661system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram

667system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram

662system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
663system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
664system.membus.snoop_fanout::min_value 0 # Request fanout histogram
665system.membus.snoop_fanout::max_value 0 # Request fanout histogram

668system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
669system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
670system.membus.snoop_fanout::min_value 0 # Request fanout histogram
671system.membus.snoop_fanout::max_value 0 # Request fanout histogram

666system.membus.snoop_fanout::total 3869897 # Request fanout histogram
667system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)

672system.membus.snoop_fanout::total 1970570 # Request fanout histogram
673system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks)

668system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)

674system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)

669system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)

675system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks)