| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.377030 # Number of seconds simulated 4sim_ticks 2377029670500 # Number of ticks simulated 5final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.377030 # Number of seconds simulated 4sim_ticks 2377029670500 # Number of ticks simulated 5final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1359798 # Simulator instruction rate (inst/s) 8host_op_rate 1465373 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2100575394 # Simulator tick rate (ticks/s) 10host_mem_usage 311664 # Number of bytes of host memory used 11host_seconds 1131.61 # Real time elapsed on the host | 7host_inst_rate 1373046 # Simulator instruction rate (inst/s) 8host_op_rate 1479650 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2121040557 # Simulator tick rate (ticks/s) 10host_mem_usage 312336 # Number of bytes of host memory used 11host_seconds 1120.69 # Real time elapsed on the host |
| 12sim_insts 1538759602 # Number of instructions simulated 13sim_ops 1658228915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1538759602 # Number of instructions simulated 13sim_ops 1658228915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 31system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory 19system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory 23system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory --- 7 unchanged lines hidden (view full) --- 32system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) |
| 40system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 39system.cpu_clk_domain.clock 500 # Clock period in ticks | 41system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 42system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 43system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 64system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 67system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 71system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 72system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses | 73system.cpu.dtb.walker.walks 0 # Table walker walks requested 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 94system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dtb.read_accesses 0 # DTB read accesses 97system.cpu.dtb.write_accesses 0 # DTB write accesses 98system.cpu.dtb.inst_accesses 0 # ITB inst accesses 99system.cpu.dtb.hits 0 # DTB hits 100system.cpu.dtb.misses 0 # DTB misses 101system.cpu.dtb.accesses 0 # DTB accesses |
| 102system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 103system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 132system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 46 # Number of system calls | 133system.cpu.itb.walker.walks 0 # Table walker walks requested 134system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 0 # ITB inst accesses 159system.cpu.itb.hits 0 # DTB hits 160system.cpu.itb.misses 0 # DTB misses 161system.cpu.itb.accesses 0 # DTB accesses 162system.cpu.workload.num_syscalls 46 # Number of system calls |
| 163system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 157system.cpu.numCycles 4754059341 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 1538759602 # Number of instructions committed 161system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 164system.cpu.num_func_calls 27330256 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 212system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 213system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 1664032481 # Class of executed instruction | 164system.cpu.numCycles 4754059341 # number of cpu cycles simulated 165system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 166system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 167system.cpu.committedInsts 1538759602 # Number of instructions committed 168system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed 169system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 170system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 171system.cpu.num_func_calls 27330256 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 216system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 217system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 218system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 219system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 220system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 221system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 222system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 223system.cpu.op_class::total 1664032481 # Class of executed instruction |
| 224system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 217system.cpu.dcache.tags.replacements 9111140 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses | 225system.cpu.dcache.tags.replacements 9111140 # number of replacements 226system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use 227system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. 228system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 229system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. 230system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. 231system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor 232system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy 233system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy 234system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 235system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id 236system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id 237system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id 238system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id 239system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 240system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 241system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses 242system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses |
| 243system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 235system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 239system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 240system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 241system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 242system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits --- 94 unchanged lines hidden (view full) --- 337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency 339system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 341system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency 343system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency | 244system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits 245system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits 246system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 247system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 248system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 249system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 250system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 251system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits --- 94 unchanged lines hidden (view full) --- 346system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency 347system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency 348system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 349system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 350system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency 351system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency 352system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency 353system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency |
| 354system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 345system.cpu.icache.tags.replacements 7 # number of replacements 346system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use 347system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. 348system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 349system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. 350system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 351system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor 352system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy 353system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy 354system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 355system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 358system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 359system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses 360system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses | 355system.cpu.icache.tags.replacements 7 # number of replacements 356system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use 357system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. 358system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 359system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. 360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 361system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor 362system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 368system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 369system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses 370system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses |
| 371system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 361system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits 362system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits 363system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits 364system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits 365system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits 366system.cpu.icache.overall_hits::total 1544564953 # number of overall hits 367system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 368system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 421system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 422system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency 425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency 427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency | 372system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits 373system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits 374system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits 375system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits 376system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits 377system.cpu.icache.overall_hits::total 1544564953 # number of overall hits 378system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 379system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 432system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 433system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 434system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency 436system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency 438system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency |
| 440system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 429system.cpu.l2cache.tags.replacements 1919027 # number of replacements 430system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use 431system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. 432system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. 433system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. 434system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. 435system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor 436system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 443system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 444system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 445system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id 446system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id 448system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 449system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses 450system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses | 441system.cpu.l2cache.tags.replacements 1919027 # number of replacements 442system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use 443system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. 444system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. 445system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. 446system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. 447system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor 448system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 455system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 457system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id 458system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id 460system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 461system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses 462system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses |
| 463system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 451system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits 452system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits 453system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits 454system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits 455system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits 456system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits 457system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 458system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 589system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency 590system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency 591system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. 592system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. 593system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 594system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. 595system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 596system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 464system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits 465system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits 466system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits 467system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits 468system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits 469system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits 470system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits 471system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits --- 130 unchanged lines hidden (view full) --- 602system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency 603system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency 604system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. 605system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. 606system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 607system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. 608system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 609system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 610system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 597system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution 600system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 621system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram 623system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) 624system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 625system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 626system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 627system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 628system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) | 611system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 616system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 617system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution 618system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 635system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram 637system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) 638system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) 639system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 640system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 641system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 642system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) |
| 643system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states |
|
| 629system.membus.trans_dist::ReadResp 1169580 # Transaction distribution 630system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution 631system.membus.trans_dist::CleanEvict 897056 # Transaction distribution 632system.membus.trans_dist::ReadExReq 782134 # Transaction distribution 633system.membus.trans_dist::ReadExResp 782134 # Transaction distribution 634system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution 635system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) 636system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden --- | 644system.membus.trans_dist::ReadResp 1169580 # Transaction distribution 645system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution 646system.membus.trans_dist::CleanEvict 897056 # Transaction distribution 647system.membus.trans_dist::ReadExReq 782134 # Transaction distribution 648system.membus.trans_dist::ReadExResp 782134 # Transaction distribution 649system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution 650system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) 651system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden --- |