| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.377030 # Number of seconds simulated 4sim_ticks 2377029670500 # Number of ticks simulated 5final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.377030 # Number of seconds simulated 4sim_ticks 2377029670500 # Number of ticks simulated 5final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 872363 # Simulator instruction rate (inst/s) 8host_op_rate 940093 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1347600333 # Simulator tick rate (ticks/s) 10host_mem_usage 317216 # Number of bytes of host memory used 11host_seconds 1763.90 # Real time elapsed on the host | 7host_inst_rate 1034140 # Simulator instruction rate (inst/s) 8host_op_rate 1114431 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1597508455 # Simulator tick rate (ticks/s) 10host_mem_usage 269992 # Number of bytes of host memory used 11host_seconds 1487.96 # Real time elapsed on the host |
| 12sim_insts 1538759602 # Number of instructions simulated 13sim_ops 1658228915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory --- 275 unchanged lines hidden (view full) --- 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 1538759602 # Number of instructions simulated 13sim_ops 1658228915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory --- 275 unchanged lines hidden (view full) --- 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 305system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks 306system.cpu.dcache.writebacks::total 3681379 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses 308system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses --- 26 unchanged lines hidden (view full) --- 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency | 303system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks 304system.cpu.dcache.writebacks::total 3681379 # number of writebacks 305system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses 306system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses 307system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 308system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 309system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 310system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses --- 26 unchanged lines hidden (view full) --- 337system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency 338system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency 339system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 340system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 341system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency 342system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency 343system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency 344system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency |
| 347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 348system.cpu.icache.tags.replacements 7 # number of replacements 349system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use 350system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. 351system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 352system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. 353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor 355system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 398system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency 400system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 401system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 402system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 404system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 405system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 345system.cpu.icache.tags.replacements 7 # number of replacements 346system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use 347system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. 348system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 349system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. 350system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 351system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor 352system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 395system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency 396system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency 397system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 400system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 401system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 402system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 406system.cpu.icache.fast_writes 0 # number of fast writes performed 407system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 408system.cpu.icache.writebacks::writebacks 7 # number of writebacks 409system.cpu.icache.writebacks::total 7 # number of writebacks 410system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 411system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 412system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 413system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 414system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 415system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 427system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency | 403system.cpu.icache.writebacks::writebacks 7 # number of writebacks 404system.cpu.icache.writebacks::total 7 # number of writebacks 405system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 406system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 407system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 408system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 409system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 410system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 421system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 422system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency 425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency 427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency |
| 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 435system.cpu.l2cache.tags.replacements 1919027 # number of replacements 436system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use 437system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. 438system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. 439system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. 440system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. 441system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor 442system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 535system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency 537system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 541system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 429system.cpu.l2cache.tags.replacements 1919027 # number of replacements 430system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use 431system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. 432system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. 433system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. 434system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. 435system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor 436system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 529system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency 530system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency 531system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 532system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 533system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 534system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 535system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 536system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 543system.cpu.l2cache.fast_writes 0 # number of fast writes performed 544system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 545system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks 546system.cpu.l2cache.writebacks::total 1021127 # number of writebacks 547system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses 548system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses 549system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses 550system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses 551system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses 552system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 591system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency 592system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency 593system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency 594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency 595system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency 596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency 597system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency 598system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency | 537system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks 538system.cpu.l2cache.writebacks::total 1021127 # number of writebacks 539system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses 540system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses 541system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses 542system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses 543system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses 544system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses --- 38 unchanged lines hidden (view full) --- 583system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency 584system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency 585system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency 586system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency 587system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency 588system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency 589system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency 590system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency |
| 599system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 600system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. 601system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. 602system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 603system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. 604system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 605system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 606system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution --- 57 unchanged lines hidden --- | 591system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. 592system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. 593system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 594system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. 595system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 596system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 597system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution --- 57 unchanged lines hidden --- |