Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.363367 # Number of seconds simulated
4sim_ticks 2363367211500 # Number of ticks simulated
5final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.363368 # Number of seconds simulated
4sim_ticks 2363368369500 # Number of ticks simulated
5final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1091670 # Simulator instruction rate (inst/s)
8host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1676685643 # Simulator tick rate (ticks/s)
10host_mem_usage 312924 # Number of bytes of host memory used
11host_seconds 1409.55 # Real time elapsed on the host

7host_inst_rate 1008024 # Simulator instruction rate (inst/s)
8host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1548215415 # Simulator tick rate (ticks/s)
10host_mem_usage 315828 # Number of bytes of host memory used
11host_seconds 1526.51 # Real time elapsed on the host

12sim_insts 1538759602 # Number of instructions simulated
13sim_ops 1658228915 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 124870144 # Number of bytes read from this memory
18system.physmem.bytes_read::total 124909568 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
22system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 1951096 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 1951712 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s)

31system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s)

33system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s)

33system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s)

36system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s)

39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 46 # Number of system calls

157system.cpu.numCycles 4726734423 # number of cpu cycles simulated

157system.cpu.numCycles 4726736739 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 1538759602 # Number of instructions committed
161system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
164system.cpu.num_func_calls 27330256 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
174system.cpu.num_mem_refs 633153380 # number of memory refs
175system.cpu.num_load_insts 458306334 # Number of load instructions
176system.cpu.num_store_insts 174847046 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 213462427 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
184system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
212system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
213system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 1664032481 # Class of executed instruction
217system.cpu.dcache.tags.replacements 9111140 # number of replacements

218system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use

218system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use

219system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.

222system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor

222system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor

224system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id

--- 17 unchanged lines hidden (view full) ---

249system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
250system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
251system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
252system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
253system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
254system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
255system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
256system.cpu.dcache.overall_misses::total 9115236 # number of overall misses

257system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles
258system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles

257system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles
258system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles

259system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles
260system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles

261system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles
262system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles
263system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles
264system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles

261system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles
262system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles
263system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles
264system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles

265system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
266system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
267system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
268system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
269system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
270system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
271system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
272system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

281system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
282system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
283system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
284system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
285system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
286system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
287system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
288system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses

289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency
290system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency

289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency
290system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency

291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency
292system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency

293system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency
294system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency
295system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency
296system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency

293system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency
294system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency
295system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency
296system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency

297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
303system.cpu.dcache.fast_writes 0 # number of fast writes performed
304system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
310system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
312system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
313system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
314system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
315system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
316system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses

317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles

317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles

319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles
320system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles
321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles

323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles

323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles

327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
334system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
336system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses

337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency
338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency

337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency
338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency

339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency

343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency

343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency

347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
348system.cpu.icache.tags.replacements 7 # number of replacements

349system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use

349system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use

350system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
351system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
352system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

354system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor

354system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor

355system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy
356system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy
357system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
361system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
362system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses

--- 5 unchanged lines hidden (view full) ---

368system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits
369system.cpu.icache.overall_hits::total 1544564953 # number of overall hits
370system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
371system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
372system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
373system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
374system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
375system.cpu.icache.overall_misses::total 638 # number of overall misses

376system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles
377system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles
378system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles
379system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles
380system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles
381system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles

376system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles
377system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles
378system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles
379system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles
380system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles
381system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles

382system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
383system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
384system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
385system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses
386system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses
387system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses
388system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
389system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
390system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
391system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
392system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
393system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses

394system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency
395system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency
396system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
397system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency
398system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
399system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency

394system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency
395system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency
396system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
397system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency
398system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
399system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency

400system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
401system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
402system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
403system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
404system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
405system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
406system.cpu.icache.fast_writes 0 # number of fast writes performed
407system.cpu.icache.cache_copies 0 # number of cache copies performed
408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
409system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
410system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
411system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
412system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
413system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses

414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles
415system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles
416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles
417system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles
418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles
419system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles

414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles
415system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles
416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles
417system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles
418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles
419system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles

420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
423system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
425system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses

426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency
427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency
428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency

426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency
427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency
428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
429system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
431system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency

432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
433system.cpu.l2cache.tags.replacements 1919018 # number of replacements

434system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use

434system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use

435system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks.
436system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks.
437system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks.

438system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit.
439system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor
440system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor
441system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor

438system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit.
439system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor
440system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor
441system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor

442system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy
443system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy
444system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy
445system.cpu.l2cache.tags.occ_percent::total 0.946295 # Average percentage of cache occupancy
446system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
447system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
448system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
449system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1084 # Occupied blocks per task id

--- 27 unchanged lines hidden (view full) ---

477system.cpu.l2cache.demand_misses::total 1951712 # number of demand (read+write) misses
478system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
479system.cpu.l2cache.overall_misses::cpu.data 1951096 # number of overall misses
480system.cpu.l2cache.overall_misses::total 1951712 # number of overall misses
481system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000 # number of ReadExReq miss cycles
482system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles
483system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles
484system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles

485system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles
486system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles

485system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles
486system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles

487system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles

488system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles
489system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles

488system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles
489system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles

490system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles

491system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles
492system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles

491system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles
492system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles

493system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses)
494system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses)
495system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
496system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
497system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses)
498system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses)
499system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses)
500system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses)

--- 14 unchanged lines hidden (view full) ---

515system.cpu.l2cache.demand_miss_rate::total 0.214100 # miss rate for demand accesses
516system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
517system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
518system.cpu.l2cache.overall_miss_rate::total 0.214100 # miss rate for overall accesses
519system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565 # average ReadExReq miss latency
520system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency
521system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency
522system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency

523system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency
524system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency

523system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency
524system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency

525system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency

526system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
527system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency

526system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
527system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency

528system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency

529system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
530system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency

529system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
530system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency

531system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
532system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
533system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
534system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
535system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
536system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
537system.cpu.l2cache.fast_writes 0 # number of fast writes performed
538system.cpu.l2cache.cache_copies 0 # number of cache copies performed

--- 12 unchanged lines hidden (view full) ---

551system.cpu.l2cache.demand_mshr_misses::total 1951712 # number of demand (read+write) MSHR misses
552system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
553system.cpu.l2cache.overall_mshr_misses::cpu.data 1951096 # number of overall MSHR misses
554system.cpu.l2cache.overall_mshr_misses::total 1951712 # number of overall MSHR misses
555system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 # number of ReadExReq MSHR miss cycles
556system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles
557system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles
558system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles

559system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles
560system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles

559system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles
560system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles

561system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles

562system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles
563system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles

562system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles
563system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles

564system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles

565system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles
566system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles

565system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles
566system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles

567system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
568system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
569system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses
570system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414013 # mshr miss rate for ReadExReq accesses
571system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses
572system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses
573system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
574system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
575system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
576system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
577system.cpu.l2cache.demand_mshr_miss_rate::total 0.214100 # mshr miss rate for demand accesses
578system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
579system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
580system.cpu.l2cache.overall_mshr_miss_rate::total 0.214100 # mshr miss rate for overall accesses
581system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 # average ReadExReq mshr miss latency
582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency
583system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency
584system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency

585system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency
586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency

585system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency
586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency

587system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency

588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
589system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency

588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
589system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency

590system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency

591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
592system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency

591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
592system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency

593system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

594system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
595system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
596system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
597system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
598system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
599system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

594system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
595system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution
596system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
600system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
601system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
602system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes)
603system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes)
604system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
605system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
606system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes)
607system.cpu.toL2Bus.snoops 1919018 # Total snoops (count)
608system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram

600system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
607system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
608system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes)
609system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes)
610system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
611system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
612system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes)
613system.cpu.toL2Bus.snoops 1919018 # Total snoops (count)
614system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram

609system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram
610system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram

615system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
616system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram

611system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

617system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

612system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
613system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram
614system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram

618system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram
619system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram
620system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

615system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

621system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

616system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
617system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

622system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
623system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram