Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.363671 # Number of seconds simulated
4sim_ticks 2363670998000 # Number of ticks simulated
5final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.363663 # Number of seconds simulated
4sim_ticks 2363662966500 # Number of ticks simulated
5final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1113267 # Simulator instruction rate (inst/s)
8host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1710076181 # Simulator tick rate (ticks/s)
10host_mem_usage 309628 # Number of bytes of host memory used
11host_seconds 1382.20 # Real time elapsed on the host

7host_inst_rate 1021163 # Simulator instruction rate (inst/s)
8host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1568591191 # Simulator tick rate (ticks/s)
10host_mem_usage 309800 # Number of bytes of host memory used
11host_seconds 1506.87 # Real time elapsed on the host

12sim_insts 1538759601 # Number of instructions simulated
13sim_ops 1658228914 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)

29system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s)

31system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s)

33system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)

33system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s)

36system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s)

39system.cpu_clk_domain.clock 500 # Clock period in ticks
40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
150system.cpu.itb.read_accesses 0 # DTB read accesses
151system.cpu.itb.write_accesses 0 # DTB write accesses
152system.cpu.itb.inst_accesses 0 # ITB inst accesses
153system.cpu.itb.hits 0 # DTB hits
154system.cpu.itb.misses 0 # DTB misses
155system.cpu.itb.accesses 0 # DTB accesses
156system.cpu.workload.num_syscalls 46 # Number of system calls

157system.cpu.numCycles 4727341996 # number of cpu cycles simulated

157system.cpu.numCycles 4727325933 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 1538759601 # Number of instructions committed
161system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
164system.cpu.num_func_calls 27330256 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
174system.cpu.num_mem_refs 633153380 # number of memory refs
175system.cpu.num_load_insts 458306334 # Number of load instructions
176system.cpu.num_store_insts 174847046 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 213462426 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
184system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
212system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
213system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 1664032480 # Class of executed instruction
217system.cpu.dcache.tags.replacements 9111140 # number of replacements

218system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use

218system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use

219system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
220system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
221system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.

222system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor

222system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit.
223system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor

224system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
225system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
227system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id

--- 17 unchanged lines hidden (view full) ---

249system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
250system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
251system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
252system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
253system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
254system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
255system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
256system.cpu.dcache.overall_misses::total 9115236 # number of overall misses

257system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
258system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
259system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
260system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
261system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
262system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
263system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
264system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles

257system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles
258system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles
259system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles
260system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles
261system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles
262system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles
263system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles
264system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles

265system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
266system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
267system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
268system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
269system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
270system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
271system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
272system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

281system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
282system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
283system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
284system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
285system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
286system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
287system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
288system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses

289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
290system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
292system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
293system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
294system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
295system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
296system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency

289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency
290system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency
291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency
292system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency
293system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency
294system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency
295system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency
296system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency

297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
303system.cpu.dcache.fast_writes 0 # number of fast writes performed
304system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
310system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
312system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
313system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
314system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
315system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
316system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses

317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
320system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles

317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles
318system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles
319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles
320system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles
321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles
324system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles
325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles
326system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles

327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
334system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
336system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses

337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency

337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency
338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency
339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency
340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency
341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency
344system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency
345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency
346system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency

347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
348system.cpu.icache.tags.replacements 7 # number of replacements

349system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use

349system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use

350system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
351system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
352system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

354system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor

354system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor

355system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy
356system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy
357system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
358system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
359system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
361system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
362system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses

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368system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
369system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
370system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
371system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
372system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
373system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
374system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
375system.cpu.icache.overall_misses::total 638 # number of overall misses

376system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
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398system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
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438system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
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449system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id
451system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id
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570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency
571system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency
572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency
573system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
575system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
578system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency

579system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
580system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
581system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
582system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
583system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
584system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
585system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
586system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
587system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
588system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
589system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
590system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
591system.cpu.toL2Bus.snoops 0 # Total snoops (count)
592system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram

593system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram

593system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram

594system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
595system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
596system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
597system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
598system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram

599system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
602system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram

599system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram

603system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

601system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

604system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
605system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram

602system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
603system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

606system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
607system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
608system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
609system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
610system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
611system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
612system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
613system.membus.trans_dist::ReadReq 1177898 # Transaction distribution

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625system.membus.snoop_fanout::stdev 0 # Request fanout histogram
626system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
627system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram
628system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
629system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
630system.membus.snoop_fanout::min_value 0 # Request fanout histogram
631system.membus.snoop_fanout::max_value 0 # Request fanout histogram
632system.membus.snoop_fanout::total 2975972 # Request fanout histogram

604system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
605system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
606system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
607system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
608system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
609system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
610system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
611system.membus.trans_dist::ReadReq 1177898 # Transaction distribution

--- 11 unchanged lines hidden (view full) ---

623system.membus.snoop_fanout::stdev 0 # Request fanout histogram
624system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
625system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram
626system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
627system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
628system.membus.snoop_fanout::min_value 0 # Request fanout histogram
629system.membus.snoop_fanout::max_value 0 # Request fanout histogram
630system.membus.snoop_fanout::total 2975972 # Request fanout histogram

633system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
634system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
635system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
636system.membus.respLayer1.utilization 0.7 # Layer utilization (%)

631system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks)
632system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
633system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks)
634system.membus.respLayer1.utilization 0.4 # Layer utilization (%)