3,5c3,5
< sim_seconds 2.377030 # Number of seconds simulated
< sim_ticks 2377029670500 # Number of ticks simulated
< final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.379922 # Number of seconds simulated
> sim_ticks 2379921906500 # Number of ticks simulated
> final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 744525 # Simulator instruction rate (inst/s)
< host_op_rate 802329 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1150119113 # Simulator tick rate (ticks/s)
< host_mem_usage 266344 # Number of bytes of host memory used
< host_seconds 2066.77 # Real time elapsed on the host
---
> host_inst_rate 802178 # Simulator instruction rate (inst/s)
> host_op_rate 864460 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1240688848 # Simulator tick rate (ticks/s)
> host_mem_usage 272000 # Number of bytes of host memory used
> host_seconds 1918.23 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
< system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory
> system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
< system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory
25,40c25,40
< system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
72c72
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
102c102
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
132c132
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
163,164c163,164
< system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 4754059341 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 4759843813 # number of cpu cycles simulated
185c185
< system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles
224c224
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
226c226
< system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use
230,233c230,233
< system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy
235,237c235,237
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id
243c243
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
266,273c266,273
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles
298,305c298,305
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency
312,313c312,313
< system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
< system.cpu.dcache.writebacks::total 3681379 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks
> system.cpu.dcache.writebacks::total 3667054 # number of writebacks
324,333c324,333
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles
344,354c344,354
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
356c356
< system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use
361,363c361,363
< system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy
371c371
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
384,389c384,389
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles
402,407c402,407
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency
422,427c422,427
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles
434,465c434,465
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 1919027 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 1938113 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits
468,469c468,469
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits
472,473c472,473
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits
475,476c475,476
< system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits
478,481c478,481
< system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses
---
> system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses
484,485c484,485
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses
487,488c487,488
< system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses
490,505c490,505
< system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses)
520,521c520,521
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses
524,525c524,525
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses
527,528c527,528
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses
530,543c530,543
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency
550,555c550,555
< system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
< system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks
> system.cpu.l2cache.writebacks::total 1031709 # number of writebacks
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses
558,559c558,559
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses
561,562c561,562
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses
564,577c564,577
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles
580,581c580,581
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses
584,585c584,585
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses
587,588c587,588
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses
590,603c590,603
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
607,608c607,608
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
610c610
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
612c612
< system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution
614c614
< system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution
623,629c623,629
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1938113 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram
631,632c631,632
< system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram
637,638c637,638
< system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks)
644,654c644,660
< system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
< system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
< system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
< system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 1176874 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution
> system.membus.trans_dist::CleanEvict 905404 # Transaction distribution
> system.membus.trans_dist::ReadExReq 793696 # Transaction distribution
> system.membus.trans_dist::ReadExResp 793696 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes)
657c663
< system.membus.snoop_fanout::samples 3869897 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 1970570 # Request fanout histogram
661c667
< system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram
666,667c672,673
< system.membus.snoop_fanout::total 3869897 # Request fanout histogram
< system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1970570 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks)
669c675
< system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks)
< sim_seconds 2.377030 # Number of seconds simulated
< sim_ticks 2377029670500 # Number of ticks simulated
< final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.379922 # Number of seconds simulated
> sim_ticks 2379921906500 # Number of ticks simulated
> final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 744525 # Simulator instruction rate (inst/s)
< host_op_rate 802329 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1150119113 # Simulator tick rate (ticks/s)
< host_mem_usage 266344 # Number of bytes of host memory used
< host_seconds 2066.77 # Real time elapsed on the host
---
> host_inst_rate 802178 # Simulator instruction rate (inst/s)
> host_op_rate 864460 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1240688848 # Simulator tick rate (ticks/s)
> host_mem_usage 272000 # Number of bytes of host memory used
> host_seconds 1918.23 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
18,19c18,19
< system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
< system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory
> system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
< system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory
25,40c25,40
< system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
42c42
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
72c72
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
102c102
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
132c132
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
163,164c163,164
< system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 4754059341 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 4759843813 # number of cpu cycles simulated
185c185
< system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles
224c224
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
226c226
< system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use
230,233c230,233
< system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy
235,237c235,237
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id
243c243
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
266,273c266,273
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles
298,305c298,305
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency
312,313c312,313
< system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
< system.cpu.dcache.writebacks::total 3681379 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks
> system.cpu.dcache.writebacks::total 3667054 # number of writebacks
324,333c324,333
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles
344,354c344,354
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
356c356
< system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use
361,363c361,363
< system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy
371c371
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
384,389c384,389
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles
402,407c402,407
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency
422,427c422,427
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles
434,465c434,465
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 1919027 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 1938113 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits
468,469c468,469
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits
472,473c472,473
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits
---
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits
475,476c475,476
< system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits
478,481c478,481
< system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses
---
> system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses
484,485c484,485
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses
487,488c487,488
< system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses
490,505c490,505
< system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses)
520,521c520,521
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses
524,525c524,525
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses
527,528c527,528
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses
530,543c530,543
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency
550,555c550,555
< system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
< system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks
> system.cpu.l2cache.writebacks::total 1031709 # number of writebacks
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses
558,559c558,559
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses
561,562c561,562
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses
564,577c564,577
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles
580,581c580,581
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses
584,585c584,585
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses
587,588c587,588
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses
590,603c590,603
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
607,608c607,608
< system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
610c610
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
612c612
< system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution
614c614
< system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution
623,629c623,629
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1938113 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram
631,632c631,632
< system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram
637,638c637,638
< system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks)
644,654c644,660
< system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
< system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
< system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
< system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 1176874 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution
> system.membus.trans_dist::CleanEvict 905404 # Transaction distribution
> system.membus.trans_dist::ReadExReq 793696 # Transaction distribution
> system.membus.trans_dist::ReadExResp 793696 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes)
657c663
< system.membus.snoop_fanout::samples 3869897 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 1970570 # Request fanout histogram
661c667
< system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram
666,667c672,673
< system.membus.snoop_fanout::total 3869897 # Request fanout histogram
< system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1970570 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks)
669c675
< system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks)