3,5c3,5
< sim_seconds 2.363367 # Number of seconds simulated
< sim_ticks 2363367211500 # Number of ticks simulated
< final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.363368 # Number of seconds simulated
> sim_ticks 2363368369500 # Number of ticks simulated
> final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1091670 # Simulator instruction rate (inst/s)
< host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1676685643 # Simulator tick rate (ticks/s)
< host_mem_usage 312924 # Number of bytes of host memory used
< host_seconds 1409.55 # Real time elapsed on the host
---
> host_inst_rate 1008024 # Simulator instruction rate (inst/s)
> host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1548215415 # Simulator tick rate (ticks/s)
> host_mem_usage 315828 # Number of bytes of host memory used
> host_seconds 1526.51 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 4726734423 # number of cpu cycles simulated
---
> system.cpu.numCycles 4726736739 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor
257,258c257,258
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles
261,264c261,264
< system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles
289,290c289,290
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency
293,296c293,296
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency
317,318c317,318
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles
323,326c323,326
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles
337,338c337,338
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency
343,346c343,346
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency
349c349
< system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use
354c354
< system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor
376,381c376,381
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles
394,399c394,399
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency
414,419c414,419
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles
426,431c426,431
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
434c434
< system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use
438,441c438,441
< system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor
485,486c485,486
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles
488,489c488,489
< system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles
491,492c491,492
< system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles
523,524c523,524
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency
526,527c526,527
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency
529,530c529,530
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency
559,560c559,560
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles
562,563c562,563
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles
565,566c565,566
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles
585,586c585,586
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency
588,589c588,589
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
591,592c591,592
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
593a594,599
> system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
609,610c615,616
< system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram
612,614c618,620
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
616,617c622,623
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
< sim_seconds 2.363367 # Number of seconds simulated
< sim_ticks 2363367211500 # Number of ticks simulated
< final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.363368 # Number of seconds simulated
> sim_ticks 2363368369500 # Number of ticks simulated
> final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1091670 # Simulator instruction rate (inst/s)
< host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1676685643 # Simulator tick rate (ticks/s)
< host_mem_usage 312924 # Number of bytes of host memory used
< host_seconds 1409.55 # Real time elapsed on the host
---
> host_inst_rate 1008024 # Simulator instruction rate (inst/s)
> host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1548215415 # Simulator tick rate (ticks/s)
> host_mem_usage 315828 # Number of bytes of host memory used
> host_seconds 1526.51 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 4726734423 # number of cpu cycles simulated
---
> system.cpu.numCycles 4726736739 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor
257,258c257,258
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles
261,264c261,264
< system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles
289,290c289,290
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency
293,296c293,296
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency
317,318c317,318
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles
323,326c323,326
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles
337,338c337,338
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency
343,346c343,346
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency
349c349
< system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use
354c354
< system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor
376,381c376,381
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles
394,399c394,399
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency
414,419c414,419
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles
426,431c426,431
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
434c434
< system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use
438,441c438,441
< system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor
485,486c485,486
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles
488,489c488,489
< system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles
491,492c491,492
< system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles
523,524c523,524
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency
526,527c526,527
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency
529,530c529,530
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency
559,560c559,560
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles
562,563c562,563
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles
565,566c565,566
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles
585,586c585,586
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency
588,589c588,589
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
591,592c591,592
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
593a594,599
> system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
609,610c615,616
< system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram
612,614c618,620
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
616,617c622,623
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram