3,5c3,5
< sim_seconds 2.363671 # Number of seconds simulated
< sim_ticks 2363670998000 # Number of ticks simulated
< final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.363663 # Number of seconds simulated
> sim_ticks 2363662966500 # Number of ticks simulated
> final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1113267 # Simulator instruction rate (inst/s)
< host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1710076181 # Simulator tick rate (ticks/s)
< host_mem_usage 309628 # Number of bytes of host memory used
< host_seconds 1382.20 # Real time elapsed on the host
---
> host_inst_rate 1021163 # Simulator instruction rate (inst/s)
> host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1568591191 # Simulator tick rate (ticks/s)
> host_mem_usage 309800 # Number of bytes of host memory used
> host_seconds 1506.87 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 4727341996 # number of cpu cycles simulated
---
> system.cpu.numCycles 4727325933 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor
257,264c257,264
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles
289,296c289,296
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency
317,326c317,326
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles
337,346c337,346
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency
349c349
< system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use
354c354
< system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor
376,381c376,381
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles
394,399c394,399
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency
414,419c414,419
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles
426,431c426,431
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
434c434
< system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use
438,442c438,442
< system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy
444c444
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy
479,489c479,489
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32381000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61822893500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 61855274500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40996230000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 40996230000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 32381000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 102851504500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 32381000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 102851504500 # number of overall miss cycles
514,524c514,524
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751 # average overall miss latency
546,556c546,556
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles
568,578c568,578
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
593c593
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
599,602c599,600
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
604,605c602,603
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
633,636c631,634
< system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
< system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
> system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
< sim_seconds 2.363671 # Number of seconds simulated
< sim_ticks 2363670998000 # Number of ticks simulated
< final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.363663 # Number of seconds simulated
> sim_ticks 2363662966500 # Number of ticks simulated
> final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1113267 # Simulator instruction rate (inst/s)
< host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1710076181 # Simulator tick rate (ticks/s)
< host_mem_usage 309628 # Number of bytes of host memory used
< host_seconds 1382.20 # Real time elapsed on the host
---
> host_inst_rate 1021163 # Simulator instruction rate (inst/s)
> host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1568591191 # Simulator tick rate (ticks/s)
> host_mem_usage 309800 # Number of bytes of host memory used
> host_seconds 1506.87 # Real time elapsed on the host
29,30c29,30
< system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s)
33,35c33,35
< system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s)
37,38c37,38
< system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s)
157c157
< system.cpu.numCycles 4727341996 # number of cpu cycles simulated
---
> system.cpu.numCycles 4727325933 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles
218c218
< system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use
222,223c222,223
< system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor
257,264c257,264
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles
289,296c289,296
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency
317,326c317,326
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles
337,346c337,346
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency
349c349
< system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use
354c354
< system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor
376,381c376,381
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles
394,399c394,399
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency
414,419c414,419
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles
426,431c426,431
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
434c434
< system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use
438,442c438,442
< system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy
444c444
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy
479,489c479,489
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32381000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61822893500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 61855274500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40996230000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 40996230000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 32381000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 102851504500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 32381000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 102851504500 # number of overall miss cycles
514,524c514,524
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751 # average overall miss latency
546,556c546,556
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles
568,578c568,578
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
593c593
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
599,602c599,600
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
604,605c602,603
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
633,636c631,634
< system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
< system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
> system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.4 # Layer utilization (%)