stats.txt (8911:4da2ea94319f) stats.txt (8983:8800b05e1cb3)
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.431420 # Number of seconds simulated
4sim_ticks 2431419954000 # Number of ticks simulated
5final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.431420 # Number of seconds simulated
4sim_ticks 2431419954000 # Number of ticks simulated
5final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1812626 # Simulator instruction rate (inst/s)
8host_op_rate 2022908 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2864161367 # Simulator tick rate (ticks/s)
10host_mem_usage 223004 # Number of bytes of host memory used
11host_seconds 848.91 # Real time elapsed on the host
7host_inst_rate 629125 # Simulator instruction rate (inst/s)
8host_op_rate 702110 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 994091440 # Simulator tick rate (ticks/s)
10host_mem_usage 230132 # Number of bytes of host memory used
11host_seconds 2445.87 # Real time elapsed on the host
12sim_insts 1538759609 # Number of instructions simulated
13sim_ops 1717270343 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 172766016 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 75006720 # Number of bytes written to this memory
17system.physmem.num_reads 2699469 # Number of read requests responded to by this memory
18system.physmem.num_writes 1171980 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39system.cpu.dtb.read_accesses 0 # DTB read accesses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42system.cpu.dtb.hits 0 # DTB hits
43system.cpu.dtb.misses 0 # DTB misses
44system.cpu.dtb.accesses 0 # DTB accesses
45system.cpu.itb.inst_hits 0 # ITB inst hits
46system.cpu.itb.inst_misses 0 # ITB inst misses
47system.cpu.itb.read_hits 0 # DTB read hits
48system.cpu.itb.read_misses 0 # DTB read misses
49system.cpu.itb.write_hits 0 # DTB write hits
50system.cpu.itb.write_misses 0 # DTB write misses
51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 46 # Number of system calls
67system.cpu.numCycles 4862839908 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.committedInsts 1538759609 # Number of instructions committed
71system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
72system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
73system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
74system.cpu.num_func_calls 27330134 # number of times a function call or return occured
75system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
76system.cpu.num_int_insts 1536941850 # number of integer instructions
77system.cpu.num_fp_insts 36 # number of float instructions
78system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
79system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
80system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
81system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
82system.cpu.num_mem_refs 660773816 # number of memory refs
83system.cpu.num_load_insts 485926770 # Number of load instructions
84system.cpu.num_store_insts 174847046 # Number of store instructions
85system.cpu.num_idle_cycles 0 # Number of idle cycles
86system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
87system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
88system.cpu.idle_fraction 0 # Percentage of idle cycles
89system.cpu.icache.replacements 7 # number of replacements
90system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
91system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
92system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
93system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
94system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
95system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor
96system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy
97system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
98system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
99system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits
100system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
101system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
102system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits
103system.cpu.icache.overall_hits::total 1544564961 # number of overall hits
104system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
105system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
106system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
107system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
108system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
109system.cpu.icache.overall_misses::total 638 # number of overall misses
110system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles
111system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles
112system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles
113system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
114system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
115system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
116system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
117system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
118system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses
119system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses
120system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses
121system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses
122system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
123system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
124system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency
126system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
127system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
128system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
129system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
130system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
131system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
12sim_insts 1538759609 # Number of instructions simulated
13sim_ops 1717270343 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 172766016 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 75006720 # Number of bytes written to this memory
17system.physmem.num_reads 2699469 # Number of read requests responded to by this memory
18system.physmem.num_writes 1171980 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 71055605 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 16214 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 30848937 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 101904542 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39system.cpu.dtb.read_accesses 0 # DTB read accesses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42system.cpu.dtb.hits 0 # DTB hits
43system.cpu.dtb.misses 0 # DTB misses
44system.cpu.dtb.accesses 0 # DTB accesses
45system.cpu.itb.inst_hits 0 # ITB inst hits
46system.cpu.itb.inst_misses 0 # ITB inst misses
47system.cpu.itb.read_hits 0 # DTB read hits
48system.cpu.itb.read_misses 0 # DTB read misses
49system.cpu.itb.write_hits 0 # DTB write hits
50system.cpu.itb.write_misses 0 # DTB write misses
51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 46 # Number of system calls
67system.cpu.numCycles 4862839908 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.committedInsts 1538759609 # Number of instructions committed
71system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
72system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
73system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
74system.cpu.num_func_calls 27330134 # number of times a function call or return occured
75system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
76system.cpu.num_int_insts 1536941850 # number of integer instructions
77system.cpu.num_fp_insts 36 # number of float instructions
78system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read
79system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written
80system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
81system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
82system.cpu.num_mem_refs 660773816 # number of memory refs
83system.cpu.num_load_insts 485926770 # Number of load instructions
84system.cpu.num_store_insts 174847046 # Number of store instructions
85system.cpu.num_idle_cycles 0 # Number of idle cycles
86system.cpu.num_busy_cycles 4862839908 # Number of busy cycles
87system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
88system.cpu.idle_fraction 0 # Percentage of idle cycles
89system.cpu.icache.replacements 7 # number of replacements
90system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use
91system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks.
92system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
93system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
94system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
95system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor
96system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy
97system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
98system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
99system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits
100system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
101system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
102system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits
103system.cpu.icache.overall_hits::total 1544564961 # number of overall hits
104system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
105system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
106system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
107system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
108system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
109system.cpu.icache.overall_misses::total 638 # number of overall misses
110system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles
111system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles
112system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles
113system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
114system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
115system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
116system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
117system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
118system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses
119system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses
120system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses
121system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses
122system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
123system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
124system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency
126system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
127system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
128system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
129system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
130system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
131system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
132system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
133system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
132system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
133system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
134system.cpu.icache.fast_writes 0 # number of fast writes performed
135system.cpu.icache.cache_copies 0 # number of cache copies performed
136system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
137system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
138system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
139system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
140system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
141system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
142system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles
143system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles
144system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles
145system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles
146system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles
147system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles
148system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
149system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
150system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
151system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency
152system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
154system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
155system.cpu.dcache.replacements 9111140 # number of replacements
156system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
157system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks.
158system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
159system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
160system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
161system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor
162system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy
163system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy
164system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits
165system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits
166system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
167system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
168system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
169system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
170system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
171system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
172system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits
173system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits
174system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits
175system.cpu.dcache.overall_hits::total 645854938 # number of overall hits
176system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
177system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
178system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
179system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
180system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
181system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
182system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
183system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
184system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles
185system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles
186system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles
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197system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
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144system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles
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146system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles
147system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles
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152system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
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169system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
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197system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
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231system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles
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233system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles
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237system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles
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241system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
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243system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency
244system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
245system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
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253system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor
254system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor
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271system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits
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277system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses
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282system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses
283system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses
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288system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles
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293system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles
294system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles
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296system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
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298system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses)
299system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses)
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301system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
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306system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
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309system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses
310system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses
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314system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses
315system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
316system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
317system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
318system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
319system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
321system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
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219system.cpu.dcache.cache_copies 0 # number of cache copies performed
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221system.cpu.dcache.writebacks::total 3061985 # number of writebacks
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223system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
224system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
225system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
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227system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
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229system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
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231system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles
232system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles
233system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles
234system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles
235system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles
236system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles
237system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles
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239system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
240system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
241system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
242system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency
243system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency
244system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
245system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency
246system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
247system.cpu.l2cache.replacements 2687066 # number of replacements
248system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use
249system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks.
250system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks.
251system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks.
252system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit.
253system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor
254system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor
255system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor
256system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy
257system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy
258system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy
259system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy
260system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
261system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits
262system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits
263system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits
264system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits
265system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits
266system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits
267system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
268system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits
269system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits
270system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
271system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits
272system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits
273system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
274system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses
275system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses
276system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses
277system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses
278system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
279system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses
280system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses
281system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
282system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses
283system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses
284system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
285system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles
286system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles
287system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles
288system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles
289system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
290system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles
291system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles
292system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
293system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles
294system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles
295system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
296system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
297system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
298system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses)
299system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses)
300system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
301system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
302system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
303system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
304system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
305system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
306system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
307system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
308system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
309system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses
310system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses
311system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
312system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses
313system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
314system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses
315system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
316system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
317system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
318system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
319system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
320system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
321system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
322system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
323system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
324system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
325system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
326system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
327system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
326system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
327system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
328system.cpu.l2cache.fast_writes 0 # number of fast writes performed
329system.cpu.l2cache.cache_copies 0 # number of cache copies performed
330system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks
331system.cpu.l2cache.writebacks::total 1171980 # number of writebacks
332system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
333system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses
334system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses
335system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses
336system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses
337system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
338system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses
339system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses
340system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
341system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses
342system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses
343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
344system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles
345system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles
346system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles
347system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles
348system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
349system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles
350system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles
351system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
352system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles
353system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles
354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
355system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses
356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses
357system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
358system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses
359system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
360system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses
361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
363system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
364system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
365system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
366system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
367system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
368system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
369
370---------- End Simulation Statistics ----------
328system.cpu.l2cache.fast_writes 0 # number of fast writes performed
329system.cpu.l2cache.cache_copies 0 # number of cache copies performed
330system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks
331system.cpu.l2cache.writebacks::total 1171980 # number of writebacks
332system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
333system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses
334system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses
335system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses
336system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses
337system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
338system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses
339system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses
340system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
341system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses
342system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses
343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
344system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles
345system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles
346system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles
347system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles
348system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
349system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles
350system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles
351system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
352system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles
353system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles
354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
355system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses
356system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses
357system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
358system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses
359system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
360system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses
361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
363system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
364system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
365system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
366system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
367system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
368system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
369
370---------- End Simulation Statistics ----------